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21. 发明申请

US20160320971A1 Memory System and Method for Differential Thermal Throttling 审中-公开
标题翻译：差分热调节的记忆系统和方法
公开(公告)号：US20160320971A1
公开(公告)日：2016-11-03
申请号：US14698511
申请日：2015-04-28
申请人： SanDisk Technologies Inc.
发明人： Evgeny Postavilsky , Gadi Vishne , Judah Gamliel Hahn
IPC分类号： G06F3/06 , G06F1/20
CPC分类号： G06F3/0604 , G06F1/206 , G06F3/0625 , G06F3/0653 , G06F3/0659 , G06F3/0679
摘要： A memory system and method for differential thermal throttling are disclosed. In one embodiment, a memory system is provided comprising a memory and a controller. The controller is configured to receive a command to perform an operation in the memory and analyze the command to determine whether thermal throttling the memory system would result in an unacceptable impact on user experience. In response to determining that thermal throttling the memory system would result in an unacceptable impact on user experience, the controller executes the command. In response to determining that thermal throttling the memory system would not result in an unacceptable impact on user experience, the controller thermal throttles the memory system. Other embodiments are provided.
摘要翻译：公开了用于差动热节流的存储系统和方法。在一个实施例中，提供了包括存储器和控制器的存储器系统。控制器被配置为接收在存储器中执行操作的命令并分析该命令以确定对该存储器系统的热量调节是否会对用户体验产生不可接受的影响。响应于确定热节流存储器系统将导致对用户体验的不可接受的影响，控制器执行命令。响应于确定存储器系统的热节流不会对用户体验造成不可接受的影响，控制器热调节存储器系统。提供其他实施例。

22. 发明申请

US20160314844A1 NATURAL THRESHOLD VOLTAGE COMPACTION WITH DUAL PULSE PROGRAM FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器的双脉冲程序的自然阈值电压
公开(公告)号：US20160314844A1
公开(公告)日：2016-10-27
申请号：US14926167
申请日：2015-10-29
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Huai-Yuan Tseng , Farookh Moogat
IPC分类号： G11C16/10
CPC分类号： G11C16/10 , G11C8/12 , G11C11/5628 , G11C11/5642 , G11C16/24 , G11C16/26 , G11C16/3459
摘要： A control circuit, in communication with non-volatile memory cells, is configured to distinguish and classify the memory cells into the different subsets of memory cells based on programming performance. Based on the classifying, the control circuit applies different programming signals to different subsets of the memory cells being programmed to a common data state.
摘要翻译：与非易失性存储器单元通信的控制电路被配置为基于编程性能将存储器单元区分和分类成不同的存储器单元子集。基于分类，控制电路将不同的编程信号应用于被编程为公共数据状态的存储器单元的不同子集。

23. 发明申请

US20160307634A1 CENTRALIZED VARIABLE RATE SERIALIZER AND DESERIALIZER FOR BAD COLUMN MANAGEMENT 有权
标题翻译：集中式可变速率串行程序和用于管道管理的DESERIALIZER
公开(公告)号：US20160307634A1
公开(公告)日：2016-10-20
申请号：US15194867
申请日：2016-06-28
申请人： SanDisk Technologies, Inc.
发明人： Wanfang TSAI , YenLung LI , Chen CHEN
IPC分类号： G11C16/26 , G11C16/34 , G11C16/04 , G11C16/10 , G11C16/16
CPC分类号： G11C29/82 , G11C16/0483 , G11C16/10 , G11C16/16 , G11C16/26 , G11C16/3404 , G11C29/808 , G11C2207/107
摘要： A memory circuit includes an array subdivided into multiple divisions, each connectable to a corresponding set of access circuitry. A serializer/deserializer circuit is connected to a data bus and the access circuitry to convert data between a (word-wise) serial format on the bus and (multi-word) parallel format for the access circuitry. Column redundancy circuitry is connect to the serializer/deserializer circuit to provide defective column information about the array. In converting data from a serial to a parallel format, the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column. In converting data from a parallel to a serial format the serializer/deserializer circuit skips words of the data in the parallel format based on the defective column information indicating that the location corresponds to a defective column.
摘要翻译：存储器电路包括细分成多个分区的阵列，每个分区可连接到对应的一组接入电路。串行器/解串器电路连接到数据总线和访问电路，用于在总线上的（逐字）串行格式和用于访问电路的（多字）并行格式之间转换数据。列冗余电路连接到串行器/解串器电路，以提供关于阵列的有缺陷的列信息。在将数据从串行格式转换为并行格式时，串行器/解串器电路基于指示位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。在将数据从并行转换为串行格式时，串行器/解串器电路基于指示该位置对应于缺陷列的缺陷列信息，以并行格式跳过数据字。

24. 发明申请

US20160300620A1 MULTIPLE BIT LINE VOLTAGE SENSING FOR NON-VOLATILE MEMORY 审中-公开
标题翻译：用于非易失性存储器的多位线电压感测
公开(公告)号：US20160300620A1
公开(公告)日：2016-10-13
申请号：US14817767
申请日：2015-08-04
申请人： SANDISK TECHNOLOGIES INC.
发明人： Deepanshu Dutta , Huai-Yuan Tseng , Dana Lee , Ken Oowada , Shih-Chung Lee
IPC分类号： G11C16/34 , G11C16/28 , G11C16/10 , G11C11/56 , G11C16/04
CPC分类号： G11C11/5642 , G11C11/5671 , G11C16/0483 , G11C16/10 , G11C16/24 , G11C16/26 , G11C16/28 , G11C16/3459 , G11C2211/5624 , G11C2211/5631 , G11C2211/5632
摘要： A non-volatile memory system comprises a plurality of memory cells arranged in a three dimensional structure and one or more control circuits in communication with the memory cells. The one or more control circuits are configured to program and verify programming for the memory cells. The one or more control circuits are configured to apply a reference voltage to the memory cells. While applying the reference voltage to the plurality of memory cells, the one or more control circuits are configured to sense whether different memory cells of the plurality of memory cells are in different data states by applying different bit line voltages to different bit lines connected to the different memory cells.
摘要翻译：非易失性存储器系统包括以三维结构排列的多个存储器单元和与存储器单元通信的一个或多个控制电路。一个或多个控制电路被配置为对存储器单元编程和验证编程。一个或多个控制电路被配置为将参考电压施加到存储器单元。在将参考电压施加到多个存储单元的同时，一个或多个控制电路被配置为通过将不同的位线电压施加到连接到多个存储单元的不同位线来检测多个存储单元的不同存储单元是否处于不同的数据状态不同的记忆体。

25. 发明申请

US20160291883A1 INHERENT ADAPTIVE TRIMMING 审中-公开
标题翻译：自适应修剪
公开(公告)号：US20160291883A1
公开(公告)日：2016-10-06
申请号：US14675261
申请日：2015-03-31
申请人： SANDISK TECHNOLOGIES INC.
发明人： Abhijeet Manohar , Daniel Tuers , Sathyanarayanan Subramanian , Judah Gamliel Hahn
IPC分类号： G06F3/06
CPC分类号： G06F3/0613 , G06F3/0656 , G06F3/0659 , G06F3/0679
摘要： A memory system may use adaptive trimming to control throughput and traffic from the host to/from the memory. The trimming parameters of memory may be adaptively changed based on the data rate from the host. The programming speed may be slowed in order to reduce wear and improve endurance. In particular, the data rate for the transfer of data from a data buffer to the memory (e.g. NAND flash) may be matched to the host data rate. This programming speed reduction may be triggered upon prediction of idle times in the host bus.
摘要翻译：存储器系统可以使用自适应调整来控制来自主机到/从存储器的吞吐量和流量。可以基于来自主机的数据速率自适应地改变存储器的修整参数。编程速度可能会减慢，以减少磨损并提高耐力。特别地，用于将数据从数据缓冲器传送到存储器（例如NAND闪存）的数据速率可以与主机数据速率相匹配。可以在预测主机总线中的空闲时间时触发该编程速度降低。

26. 发明申请

US20160277649A1 MODULAR FASHION ACCESSORY 有权
标题翻译：模块化时尚配件
公开(公告)号：US20160277649A1
公开(公告)日：2016-09-22
申请号：US14678511
申请日：2015-04-03
申请人： SANDISK TECHNOLOGIES INC.
发明人： ELLA TARAN KATZ , YARON BAR , GRACE HINA LEE , KYLE NATHEN SWEN , JUNG GEUN TAK
IPC分类号： H04N5/225 , H01R13/516 , H04N5/232 , H01R25/00
CPC分类号： H04N5/2257 , A44C5/0084 , A44C15/005 , A45F5/00 , A45F2005/006 , A45F2005/008 , A45F2200/0533 , G03B17/56 , G03B2217/007 , H01R13/516 , H01R25/00 , H04N5/2251 , H04N5/232 , H04N5/23241
摘要： A particular apparatus includes a first electronic component, a second electronic component, and a connecting element that is detachably connectable to the first electronic component and to the second electronic component. The first electronic component is connectable via the connecting element to the second electronic component to form a wearable item. The first electronic component includes a camera, the second electronic component includes an energy storage component, and the first electronic component is configured to receive power from the second electronic component via the connecting element.
摘要翻译：特定的装置包括第一电子部件，第二电子部件和可拆卸地连接到第一电子部件和第二电子部件的连接元件。第一电子部件可经由连接元件连接到第二电子部件以形成可穿戴物品。第一电子部件包括相机，第二电子部件包括能量存储部件，并且第一电子部件构造成经由连接元件从第二电子部件接收电力。

27. 发明申请

US20160266928A1 TASK QUEUES 审中-公开
标题翻译：任务队伍
公开(公告)号：US20160266928A1
公开(公告)日：2016-09-15
申请号：US14693685
申请日：2015-04-22
申请人： SANDISK TECHNOLOGIES INC.
发明人： YORAM RIMONI
IPC分类号： G06F9/48
CPC分类号： G06F9/4881 , G06F3/0601 , G06F9/5011 , G06F9/5016 , G06F9/5038 , G06F9/5044 , G06F2209/5021
摘要： A data storage device may be configured to use multiple task queues to schedule tasks. The multiple task queues may be configured based on an architecture of the data storage device. In some implementations, the multiple task queues may be used to organize tasks received from an access device. In other implementations, the multiple task queues may be used to identify tasks, and identification of the tasks may be associated with an order of execution of the tasks.
摘要翻译：数据存储设备可以被配置为使用多个任务队列来调度任务。可以基于数据存储设备的架构来配置多个任务队列。在一些实现中，多个任务队列可以用于组织从接入设备接收的任务。在其他实现中，多个任务队列可以用于识别任务，并且任务的标识可以与任务的执行顺序相关联。

28. 发明申请

US20160254048A1 SENSE AMPLIFIER LOCAL FEEDBACK TO CONTROL BIT LINE VOLTAGE 有权
标题翻译： SENSE放大器本地反馈控制位线电压
公开(公告)号：US20160254048A1
公开(公告)日：2016-09-01
申请号：US15151359
申请日：2016-05-10
申请人： SANDISK TECHNOLOGIES INC.
发明人： Chang Siau , Xiaowei Jiang , Yingchang Chen
IPC分类号： G11C13/00
CPC分类号： G11C13/004 , G11C7/04 , G11C7/062 , G11C7/067 , G11C7/12 , G11C7/14 , G11C11/5642 , G11C13/0069 , G11C16/24 , G11C16/26 , G11C2013/0042 , G11C2013/0045 , G11C2207/063
摘要： Methods for precharging bit lines using closed-loop feedback are described. In one embodiment, a sense amplifier may include a bit line precharge circuit for setting a bit line to a read voltage prior to sensing a memory cell connected to the bit line. The bit line precharge circuit may include a first transistor in a source-follower configuration with a first gate and a first source node electrically coupled to the bit line. By applying local feedback from the first source node to the first gate, the bit line settling time may be reduced. In some cases, a first voltage applied to the first gate may be determined based on a first current drawn from the first bit line. Thus, the first voltage applied to the first gate may vary over time depending on the conductivity of a selected memory cell connected to the bit line.
摘要翻译：描述了使用闭环反馈对位线进行预充电的方法。在一个实施例中，读出放大器可以包括位线预充电电路，用于在感测连接到位线的存储器单元之前将位线设置为读取电压。位线预充电电路可以包括具有第一栅极的源极跟随器配置的第一晶体管和电耦合到位线的第一源节点。通过将来自第一源节点的本地反馈应用于第一门，可以减少位线建立时间。在一些情况下，施加到第一栅极的第一电压可以基于从第一位线汲取的第一电流来确定。因此，施加到第一栅极的第一电压可以随时间而变化，这取决于连接到位线的所选择的存储器单元的电导率。

29. 发明申请

US20160239373A1 MULTI-DIE STATUS MODE FOR NON-VOLATILE STORAGE 审中-公开
标题翻译：用于非易失存储的多模态状态
公开(公告)号：US20160239373A1
公开(公告)日：2016-08-18
申请号：US15042169
申请日：2016-02-12
申请人： SanDisk Technologies Inc.
发明人： Grishma Shah , Jack Frayer
IPC分类号： G06F11/07
CPC分类号： G06F11/0793 , G06F11/073 , G06F11/0751 , G06F11/079
摘要： Systems and methods are provided for acquiring status information from a plurality of memory die. An apparatus is provided that includes a plurality of memory die and a memory controller. The memory controller is configured to broadcast a first status command to the plurality of memory die, receive a first status response concurrently from the plurality of memory die based on the first status command, and send a repair command to one or more of the plurality of memory die in response to the first status response not satisfying first predetermined status criteria.
摘要翻译：提供了用于从多个存储管芯获取状态信息的系统和方法。提供了一种包括多个存储器管芯和存储器控制器的装置。存储器控制器被配置为向多个存储管芯广播第一状态命令，基于第一状态命令从多个存储器管芯同时接收第一状态响应，并且向多个存储器管芯中的一个或多个发送修复命令存储器针对不满足第一预定状态标准的第一状态响应而死机。

30. 发明申请

US20160225461A1 Memory System and Method for Reducing Read Disturb Errors 有权
标题翻译：用于减少读取干扰的存储器系统和方法
公开(公告)号：US20160225461A1
公开(公告)日：2016-08-04
申请号：US14675107
申请日：2015-03-31
申请人： SanDisk Technologies Inc.
发明人： Daniel E. Tuers , Abhijeet Manohar , Nicholas Thomas , Jonathan Hsu
IPC分类号： G11C16/34 , G11C11/56 , G11C16/26 , G11C14/00
CPC分类号： G11C16/3427 , G11C11/5642 , G11C16/26 , G11C16/3431
摘要： A memory system and method for reducing read disturb errors are disclosed. In one embodiment, a memory system is provided comprising a plurality of blocks of memory and a controller. The controller is configured to detect a read disturb error in a block, identify data that caused the read disturb error, and move the data that caused the read disturb error to a block with a higher read endurance. This can be done by assigning read counters to blocks to determine frequently-read data, and storing that data in a separate block until it is less frequently read and will likely not cause additional read disturb errors.
摘要翻译：公开了一种用于减少读扰扰误差的存储系统和方法。在一个实施例中，提供了包括多个存储器块和控制器的存储器系统。控制器被配置为检测块中的读取干扰错误，识别导致读取干扰错误的数据，并将引起读取干扰错误的数据移动到具有较高读取耐久性的块。这可以通过将读计数器分配给块来确定频繁读取的数据，并将该数据存储在单独的块中，直到其被更少地读取并且可能不会引起额外的读取干扰错误。

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