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1. 发明申请

US20160211025A1 SEMICONDUCTOR MEMORY DEVICE AND OPERATING METHOD THEREOF 有权
标题翻译：半导体存储器件及其工作方法
公开(公告)号：US20160211025A1
公开(公告)日：2016-07-21
申请号：US14723168
申请日：2015-05-27
申请人： SK hynix Inc.
发明人： Byoung In JOO , Byoung Young KIM
IPC分类号： G11C16/10 , G11C16/26 , G11C16/08
CPC分类号： G11C16/10 , G11C5/02 , G11C11/5628 , G11C11/5642 , G11C16/26 , G11C16/32 , G11C2211/5631 , G11C2211/5648
摘要： The invention relates to a semiconductor memory device and an operating method thereof. The semiconductor memory device includes a first plane and a second plane each including a plurality of memory blocks, a first read and write circuit and a second read and write circuit suitable for sensing and temporarily storing data programmed into the first and second planes, respectively, and a control logic suitable for controlling the first and second read and write circuits to perform a read operation on the first and second planes, respectively, wherein the control logic controls the first and second read and write circuits to set the temporarily stored data as setting data, performs a new read operation to store new data, or maintains the temporarily stored data, depending on whether the first and second planes are in an LSB program state or an MSB program state.
摘要翻译：本发明涉及一种半导体存储器件及其操作方法。半导体存储器件包括第一平面和第二平面，每个平面包括多个存储块，第一读取和写入电路以及第二读取和写入电路，分别适于感测和临时存储编程到第一和第二平面中的数据，以及适于控制第一和第二读取和写入电路以分别在第一和第二平面上执行读取操作的控制逻辑，其中控制逻辑控制第一和第二读取和写入电路以将临时存储的数据设置为设置数据，执行新的读取操作以存储新数据，或者根据第一和第二平面是处于LSB编程状态还是MSB程序状态来维护临时存储的数据。

2. 发明申请

US20120250415A1 SIMULTANEOUS MULTI-STATE READ OR VERIFY IN NON-VOLATILE STORAGE 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US20120250415A1
公开(公告)日：2012-10-04
申请号：US13491166
申请日：2012-06-07
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

3. 发明授权

US08233324B2 Simultaneous multi-state read or verify in non-volatile storage 有权
标题翻译：在非易失性存储中同时进行多状态读取或验证
公开(公告)号：US08233324B2
公开(公告)日：2012-07-31
申请号：US12732121
申请日：2010-03-25
申请人： Eran Sharon , Yan Li , Nima Mokhlesi
发明人： Eran Sharon , Yan Li , Nima Mokhlesi
IPC分类号： G11C16/04 , G11C16/06
CPC分类号： G11C16/3459 , G11C11/5642 , G11C16/0483 , G11C16/3454 , G11C2211/5624 , G11C2211/5631
摘要： Methods and devices for simultaneously verifying or reading multiple states in non-volatile storage are disclosed. Methods and devices for efficiently reducing or eliminating cross-coupling effects in non-volatile storage are disclosed. Methods and devices for efficiently performing reads at a number of voltages to search for the threshold voltage of a memory cell are disclosed. Memory cells on different NAND strings that are read at the same time may be tested for different threshold voltage levels. Memory cells may be tested for different threshold voltages by applying different gate-to-source voltages to memory cells being tested for different threshold voltages. Memory cells may be tested for different threshold voltages by applying different drain to source voltages to the memory cells. Different amounts of compensation for cross-coupling affects may be applied to memory cells on different NAND strings that are read or programmed at the same time.
摘要翻译：公开了用于同时验证或读取非易失性存储器中的多个状态的方法和装置。公开了用于有效地减少或消除非易失性存储器中的交叉耦合效应的方法和装置。公开了用于有效执行多个电压读取以搜索存储器单元的阈值电压的方法和装置。可以在不同的NAND串上同时读取的存储单元测试不同的阈值电压电平。可以通过对不同阈值电压进行测试的存储器单元施加不同的栅极至源极电压来对不同的阈值电压测试存储器单元。可以通过对存储器单元施加不同的漏极到源极电压来对不同的阈值电压测试存储器单元。交叉耦合影响的不同量的补偿可以应用于同时读取或编程的不同NAND串上的存储单元。

4. 发明申请

US20110062409A1 PHASE CHANGE MEMORY STRUCTURE WITH MULTIPLE RESISTANCE STATES AND METHODS OF PROGRAMMING AND SENSING 有权
标题翻译：具有多种电阻状态的相变记忆结构及编程和感测方法
公开(公告)号：US20110062409A1
公开(公告)日：2011-03-17
申请号：US12949844
申请日：2010-11-19
申请人： Jun Liu , Mike Violette
发明人： Jun Liu , Mike Violette
IPC分类号： H01L45/00 , H01L21/02
CPC分类号： G11C11/56 , G11C11/5678 , G11C13/0004 , G11C2211/5631 , G11C2211/5632 , G11C2211/5634 , H01L45/06 , H01L45/1226 , H01L45/1233 , H01L45/144 , H01L45/165 , H01L45/1675 , Y10S977/754
摘要： A phase change memory structure with multiple resistance states and methods of forming, programming, and sensing the same. The memory structure includes two or more phrase change elements provided between electrodes. Each phase change element has a respective resistance curve as a function of programming voltage which is shifted relative to the resistance curves of other phase change elements. In one example structure using two phase change elements, the memory structure is capable of switching among four resistance states.
摘要翻译：具有多个电阻状态的相变存储器结构及其形成，编程和感测方法。存储器结构包括在电极之间提供的两个或更多个短语改变元件。每个相变元件具有作为编程电压的函数的相应电阻曲线，其相对于其它相变元件的电阻曲线偏移。在使用两个相变元件的一个示例结构中，存储器结构能够在四个电阻状态之间切换。

5. 发明申请

US20100271875A1 Compensating for Variations in Memory Cell Programmed State Distributions 有权
标题翻译：补偿内存单元编程状态分布的变化
公开(公告)号：US20100271875A1
公开(公告)日：2010-10-28
申请号：US12428002
申请日：2009-04-22
申请人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
发明人： Chulmin Jung , Yong Lu , Harry Hongyue Liu
IPC分类号： G11C16/02 , G11C16/04 , G11C16/06
CPC分类号： G11C11/5642 , G11C16/0483 , G11C2211/5631 , G11C2211/5632
摘要： Method and apparatus for compensating for variations in memory cell programmed state distributions, such as but not limited to a non-volatile memory formed of NAND configured Flash memory cells. In accordance with various embodiments, a memory block is formed from a plurality of memory cells that are arranged into rows and columns within the memory block, each memory cell configured to have a programmed state. A selected row of the memory block is read by concurrently applying a stepped sequence of threshold voltages to each memory cell along the selected row while sequentially decoupling read current from groups of memory cells along the selected row as the programmed states of said groups of cells are successively determined.
摘要翻译：用于补偿存储器单元编程状态分布的变化的方法和装置，例如但不限于由NAND配置的闪存单元形成的非易失性存储器。根据各种实施例，存储器块由多个存储器单元形成，多个存储器单元被布置成存储器块内的行和列，每个存储器单元被配置为具有编程状态。存储器块的选定行通过沿着所选择的行并行地向每个存储器单元施加阶梯式序列来读取，同时沿着所选行的顺序地将读取电流与存储器单元组分离，因为所述单元组的编程状态为先后确定。

6. 发明授权

US07613045B2 Operation sequence and commands for measuring threshold voltage distribution in memory 有权
标题翻译：用于测量存储器中阈值电压分布的操作顺序和命令
公开(公告)号：US07613045B2
公开(公告)日：2009-11-03
申请号：US11945120
申请日：2007-11-26
申请人： Mark Murin , Mark Shlick , Menahem Lasser , Cuong Trinh
发明人： Mark Murin , Mark Shlick , Menahem Lasser , Cuong Trinh
IPC分类号： G11C16/06
CPC分类号： G11C16/0483 , G11C11/5642 , G11C16/26 , G11C2211/5631 , G11C2211/5634
摘要： A memory device generates one or more read reference voltages rather than being explicitly supplied with each read reference voltage from an external host controller. The technique involves providing a command to the memory device that causes a reading of a set of storage elements by the memory device using a reference voltage which is different than a reference voltage used in a previous reading, where the new read reference value is not explicitly set outside the memory device. In one implementation, the memory device is provided with an initial reference voltage and a step size for generating additional reference voltages. The technique can be used, e.g., in determining a threshold voltage distribution of a set of storage elements. In this case, a voltage sweep can be applied to a word line associated with the set of storage elements, and data obtained based on the number of conductive storage elements.
摘要翻译：存储器件产生一个或多个读取参考电压，而不是明确地提供来自外部主机控制器的每个读取参考电压。该技术涉及向存储器件提供命令，其使得存储器件使用不同于先前读取中使用的参考电压的参考电压来读取一组存储元件，其中新的读取参考值不是明确的设置在存储设备外面。在一个实现中，存储器件被提供有初始参考电压和用于产生附加参考电压的步长。该技术可以用于例如确定一组存储元件的阈值电压分布。在这种情况下，可以对与该组存储元件相关联的字线施加电压扫描，并且可以基于导电存储元件的数量获得的数据。

7. 发明授权

US07542338B2 Method for reading a multi-level passive element memory cell array 有权
标题翻译：读取多级无源元件存储单元阵列的方法
公开(公告)号：US07542338B2
公开(公告)日：2009-06-02
申请号：US11461367
申请日：2006-07-31
申请人： Roy E. Scheuerlein , Tyler J. Thorp , Luca G. Fasoli
发明人： Roy E. Scheuerlein , Tyler J. Thorp , Luca G. Fasoli
IPC分类号： G11C16/04
CPC分类号： G11C17/16 , G11C11/565 , G11C11/5685 , G11C11/5692 , G11C13/0007 , G11C13/004 , G11C17/18 , G11C2013/0054 , G11C2211/5631 , G11C2211/5634 , G11C2213/32 , G11C2213/72
摘要： A four level passive element cell has memory states corresponding to decreasing resistance levels, which are preferably mapped respectively to data states 11, 01, 00, and 10 . The LSB and MSB are preferably mapped as part of different pages. To discriminate between memory cell states, the selected bit line current is sensed for at least two different combinations of reference current level and read bias voltage. A mid-level reference is used to read the LSB. When reading the MSB, a first reference between the 10 and 00 data states, and a second reference between 01 and 11 data states may be used, and the mid-level reference need not be used. In certain embodiments, the bit line current may be simultaneously compared against the first and second references, without requiring a delay to stabilize the bit line current to a different value, and the MSB generated accordingly.
摘要翻译：四级无源元件单元具有对应于降低电阻电平的存储器状态，其优选地分别映射到数据状态11,01,00和10。优选地将LSB和MSB映射为不同页面的一部分。为了区分存储单元状态，对于参考电流电平和读取偏置电压的至少两种不同的组合来检测所选择的位线电流。中间级参考用于读取LSB。当读取MSB时，可以使用10和00数据状态之间的第一个参考，并且可以使用01和11数据状态之间的第二个参考，并且不需要使用中间级参考。在某些实施例中，位线电流可以同时与第一和第二参考值进行比较，而不需要延迟来将位线电流稳定到不同的值，并且相应地生成MSB。

8. 发明申请

US20070121368A1 PROGRAMMABLE MEMORY DEVICE CIRCUIT 有权
标题翻译：可编程存储器件电路
公开(公告)号：US20070121368A1
公开(公告)日：2007-05-31
申请号：US11555560
申请日：2006-11-01
申请人： Nad Gilbert
发明人： Nad Gilbert
IPC分类号： G11C11/00
CPC分类号： G11C13/0011 , G11C11/5614 , G11C13/0069 , G11C2013/0066 , G11C2013/0078 , G11C2211/5631
摘要： Circuits for writing, reading, and erasing a programmable metallization cell are disclosed. The programming circuits compensate for parasitic capacitance and/or parasitic resistance. The parasitic resistance and/or capacitance is compensated for using a feedback loop or a time current filter. Various circuits also measure a switching speed of the programmable metallization cell.
摘要翻译：公开了用于写入，读取和擦除可编程金属化电池的电路。编程电路补偿寄生电容和/或寄生电阻。使用反馈回路或时间电流滤波器补偿寄生电阻和/或电容。各种电路还测量可编程金属化单元的切换速度。

9. 发明授权

US07082056B2 Flash memory device and architecture with multi level cells 有权
标题翻译：闪存设备和具有多级单元的架构
公开(公告)号：US07082056B2
公开(公告)日：2006-07-25
申请号：US10800228
申请日：2004-03-12
申请人： Ben Wei Chen , Augustine W. Chang
发明人： Ben Wei Chen , Augustine W. Chang
IPC分类号： G11C16/06
CPC分类号： G11C11/5642 , G11C7/1006 , G11C2211/5631 , G11C2211/5634
摘要： A FLASH memory has an array of FLASH cells that each store N multiple bits of information as charge stored on a floating gate. Reference voltages or currents are generated for each boundary between the 2N states or levels and for an upper limit and a lower limit reference for each state. A selected bit line driven by a selected FLASH cell generates a sense node that is compared to a full range of 3*2N−1 comparators in parallel. The compare results are decoded to determine which state is read from the selected FLASH cell. An in-range signal is activated when the sense node is between the upper and lower limit references. The target programming count or programming pulses is adjusted during calibration to sense in the middle of the upper and lower limit references. Margin between references is adjusted by calibration codes that select currents for summing.
摘要翻译： FLASH存储器具有闪存单元的阵列，每个存储N个多位信息作为存储在浮动栅极上的电荷。对于两个状态或电平之间的每个边界以及每个状态的上限和下限参考产生参考电压或电流。由所选择的FLASH单元驱动的所选位线产生与3×2×N + 1比较器的全范围并行比较的感测节点。解码比较结果以确定从所选择的FLASH单元读取哪个状态。当感测节点在上限和下限参考之间时，范围内信号被激活。在校准期间调整目标编程计数或编程脉冲，以在上限和下限参考值的中间进行感测。参考值之间的余量是通过选择用于求和的电流的校准码进行调整的。

10. 发明申请

US20050243601A1 Highly compact Eprom and flash EEprom devices 审中-公开
标题翻译：高度紧凑的Eprom和闪存EEprom设备
公开(公告)号：US20050243601A1
公开(公告)日：2005-11-03
申请号：US11114360
申请日：2005-04-26
申请人： Eliyahou Harari
发明人： Eliyahou Harari
IPC分类号： G11C11/34 , G11C11/56 , G11C16/04 , G11C16/34 , G11C29/00 , H01L21/28 , H01L21/336 , H01L21/8247 , H01L27/115 , H01L29/788
CPC分类号： H01L27/11519 , G11C11/5621 , G11C11/5628 , G11C11/5635 , G11C11/5642 , G11C16/0425 , G11C16/349 , G11C16/3495 , G11C29/00 , G11C29/765 , G11C29/82 , G11C2211/5613 , G11C2211/5631 , G11C2211/5634 , G11C2211/5644 , H01L27/115 , H01L27/11517 , H01L27/11521 , H01L29/40114 , H01L29/66825 , H01L29/7881 , H01L29/7885 , H01L2924/0002 , Y10S438/964 , H01L2924/00
摘要： Structures, methods of manufacturing and methods of use of electrically programmable read only memories (EPROM) and flash electrically erasable and programmable read only memories (EEPROM) include split channel and other cell configurations. An arrangement of elements and cooperative processes of manufacture provide self-alignment of the elements. An intelligent programming technique allows each memory cell to store more than the usual one bit of information. An intelligent erase algorithm prolongs the useful life of the memory cells. Use of these various features provides a memory having a very high storage density and a long life, making it particularly useful as a solid state memory in place of magnetic disk storage devices in computer systems.
摘要翻译：电气可编程只读存储器（EPROM）和闪存电可擦除可编程只读存储器（EEPROM）的结构，制造方法和使用方法包括分离通道和其他单元配置。元件和协调制造工艺的布置提供元件的自我对准。智能编程技术允许每个存储器单元存储比通常的一位信息。智能擦除算法可延长存储单元的使用寿命。使用这些各种特征提供了具有非常高的存储密度和长寿命的存储器，使得其作为固态存储器代替计算机系统中的磁盘存储装置是特别有用的。

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