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21. 发明授权

US11056493B2 Semiconductor structures with deep trench capacitor and methods of manufacture 有权
公开(公告)号：US11056493B2
公开(公告)日：2021-07-06
申请号：US16295505
申请日：2019-03-07
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
IPC分类号： H01L27/108 , H01L27/07 , H01L27/12 , H01L29/94 , H01L21/28 , H01L29/78 , H01L21/84 , H01L29/66 , G06F30/30 , G06F30/39 , G06F30/392 , G06F30/10 , H01L49/02 , H01L29/04 , H01L29/06 , H01L29/51 , H01L27/06
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

22. 发明申请

US20200075714A1 SELF-FORMING SPACERS USING OXIDATION 审中-公开
公开(公告)号：US20200075714A1
公开(公告)日：2020-03-05
申请号：US16674025
申请日：2019-11-05
申请人： International Business Machines Corporation
发明人： Kevin K. Chan , Masaharu Kobayashi , Effendi Leobandung
IPC分类号： H01L29/06 , H01L29/78 , H01L21/38 , H01L29/66 , H01L21/02 , H01L21/34
摘要： A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.

23. 发明申请

US20170117281A1 SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE 审中-公开
公开(公告)号：US20170117281A1
公开(公告)日：2017-04-27
申请号：US15399057
申请日：2017-01-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
IPC分类号： H01L27/108 , H01L49/02 , H01L29/06 , H01L29/51 , H01L21/84 , H01L29/04 , G06F17/50 , H01L27/12
CPC分类号： H01L27/10832 , G06F17/5045 , G06F17/5068 , G06F17/5072 , H01L21/84 , H01L21/845 , H01L27/0629 , H01L27/0733 , H01L27/10826 , H01L27/10829 , H01L27/10858 , H01L27/10867 , H01L27/10879 , H01L27/1203 , H01L27/1211 , H01L28/40 , H01L29/04 , H01L29/0649 , H01L29/517 , H01L29/66181 , H01L29/945
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.

24. 发明申请

US20170025418A1 SEMICONDUCTOR STRUCTURES WITH DEEP TRENCH CAPACITOR AND METHODS OF MANUFACTURE 审中-公开
标题翻译：具有深度电容电容器的半导体结构及其制造方法
公开(公告)号：US20170025418A1
公开(公告)日：2017-01-26
申请号：US15285520
申请日：2016-10-05
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kevin K. Chan , Sivananda K. Kanakasabapathy , Babar A. Khan , Masaharu Kobayashi , Effendi Leobandung , Theodorus E. Standaert , Xinhui Wang
IPC分类号： H01L27/108
CPC分类号： H01L27/10832 , G06F17/5045 , G06F17/5068 , G06F17/5072 , H01L21/84 , H01L21/845 , H01L27/0629 , H01L27/0733 , H01L27/10826 , H01L27/10829 , H01L27/10858 , H01L27/10867 , H01L27/10879 , H01L27/1203 , H01L27/1211 , H01L28/40 , H01L29/04 , H01L29/0649 , H01L29/517 , H01L29/66181 , H01L29/945
摘要： An integrated FinFET and deep trench capacitor structure and methods of manufacture are disclosed. The method includes forming at least one deep trench capacitor in a silicon on insulator (SOI) substrate. The method further includes simultaneously forming polysilicon fins from material of the at least one deep trench capacitor and SOI fins from the SOI substrate. The method further includes forming an insulator layer on the polysilicon fins. The method further includes forming gate structures over the SOI fins and the insulator layer on the polysilicon fins.
摘要翻译：公开了一种集成的FinFET和深沟槽电容器结构及其制造方法。该方法包括在绝缘体上硅（SOI）衬底上形成至少一个深沟槽电容器。该方法还包括从SOI衬底同时从至少一个深沟槽电容器的材料和SOI散热片形成多晶硅鳍片。该方法还包括在多晶硅鳍片上形成绝缘体层。该方法还包括在多晶硅鳍片上的SOI散热片和绝缘体层上形成栅极结构。

25. 发明申请

US20160322264A1 FIN FIELD EFFECT TRANSISTOR INCLUDING A STRAINED EPITAXIAL SEMICONDUCTOR SHELL 有权
公开(公告)号：US20160322264A1
公开(公告)日：2016-11-03
申请号：US15207056
申请日：2016-07-11
申请人： International Business Machines Corporation
发明人： Kevin K. Chan , Young-Hee Kim , Masaharu Kobayashi , Jinghong Li , Dae-Gyu Park
IPC分类号： H01L21/84 , H01L29/06 , H01L21/16 , H01L21/02 , H01L21/265
CPC分类号： H01L21/845 , H01L21/02524 , H01L21/02529 , H01L21/02532 , H01L21/02598 , H01L21/02636 , H01L21/165 , H01L21/26513 , H01L27/1211 , H01L29/0649 , H01L29/1054 , H01L29/66795 , H01L29/7849 , H01L29/785
摘要： A semiconductor fin including a single crystalline semiconductor material is formed on a dielectric layer. A semiconductor shell including an epitaxial semiconductor material is formed on all physically exposed surfaces of the semiconductor fin by selective epitaxy, which deposits the semiconductor material only on semiconductor surfaces and not on dielectric surfaces. The epitaxial semiconductor material can be different from the single crystalline semiconductor material, and the semiconductor shell can be bilaterally strained due to lattice mismatch. A fin field effect transistor including a strained channel can be formed. Further, the semiconductor shell can advantageously alter properties of the source and drain regions, for example, by allowing incorporation of more dopants or by facilitating a metallization process.

26. 外观设计

USD736586S1 Clamping device 有权
公开(公告)号：USD736586S1
公开(公告)日：2015-08-18
申请号：US29479495
申请日：2014-01-16
申请人： SMC CORPORATION
设计人： Chiaki Fukui , Kazuyoshi Takahashi , Hideki Sasaki , Masaharu Kobayashi

27. 发明授权

US09054192B1 Integration of Ge-containing fins and compound semiconductor fins 有权
标题翻译：含锗翅片和化合物半导体翅片的集成
公开(公告)号：US09054192B1
公开(公告)日：2015-06-09
申请号：US14135662
申请日：2013-12-20
申请人： International Business Machines Corporation
发明人： Kevin K. Chan , Cheng-Wei Cheng , Young-Hee Kim , Masaharu Kobayashi , Effendi Leobandung , Dae-Gyu Park , Devendra K. Sadana
IPC分类号： H01L29/76 , H01L27/12 , H01L21/336 , H01L29/78 , H01L21/84
CPC分类号： H01L29/0692 , H01L21/308 , H01L21/845 , H01L27/1211 , H01L29/16 , H01L29/785
摘要： A stack of a germanium-containing layer and a dielectric cap layer is formed on an insulator layer. The stack is patterned to form germanium-containing semiconductor fins and germanium-containing mandrel structures with dielectric cap structures thereupon. A dielectric masking layer is deposited and patterned to mask the germanium-containing semiconductor fins, while physically exposing sidewalls of the germanium-containing mandrel structures. A ring-shaped compound semiconductor fin is formed around each germanium-containing mandrel structure by selective epitaxy of a compound semiconductor material. A center portion of each germanium-containing mandrel can be removed to physically expose inner sidewalls of the ring-shaped compound semiconductor fin. A high-mobility compound semiconductor layer can be formed on physically exposed surfaces of the ring-shaped compound semiconductor fin. The dielectric masking layer and fin cap dielectrics can removed to provide germanium-containing semiconductor fins and compound semiconductor fins.
摘要翻译：在绝缘体层上形成含锗层和电介质盖层的堆叠。将叠层图案化以形成含有锗的半导体鳍片和具有介电帽结构的含锗芯棒结构。沉积并图案化介电掩模层以掩蔽含锗的半导体散热片，同时物理地暴露含锗芯棒结构的侧壁。通过化合物半导体材料的选择性外延形成围绕每个含锗心轴结构的环状化合物半导体鳍片。可以去除每个含锗心轴的中心部分以物理地暴露环形化合物半导体鳍片的内侧壁。高迁移率化合物半导体层可以形成在环状化合物半导体鳍片的物理暴露表面上。可以去除电介质掩模层和鳍帽电介质以提供含锗半导体鳍片和化合物半导体鳍片。

28. 发明授权

US08941147B2 Transistor formation using cold welding 有权
标题翻译：晶体管形成采用冷焊
公开(公告)号：US08941147B2
公开(公告)日：2015-01-27
申请号：US13660497
申请日：2012-10-25
申请人： International Business Machines Corporation
发明人： Cheng-Wei Cheng , Shu-Jen Han , Masaharu Kobayashi , Ko-Tao Lee , Devendra K. Sadana , Kuen-Ting Shiu
IPC分类号： H01L29/66
CPC分类号： H01L24/89 , H01L21/02381 , H01L21/02389 , H01L21/6835 , H01L24/03 , H01L24/05 , H01L24/08 , H01L24/80 , H01L24/92 , H01L29/78603 , H01L29/78681 , H01L2221/68363 , H01L2221/68377 , H01L2221/68381 , H01L2224/0345 , H01L2224/03452 , H01L2224/0361 , H01L2224/03914 , H01L2224/05617 , H01L2224/05639 , H01L2224/05644 , H01L2224/05647 , H01L2224/05655 , H01L2224/05664 , H01L2224/08145 , H01L2224/08225 , H01L2224/08245 , H01L2224/80004 , H01L2224/80006 , H01L2224/80052 , H01L2224/80201 , H01L2224/80203 , H01L2224/80379 , H01L2224/80801 , H01L2224/8083 , H01L2224/80894 , H01L2224/9202 , H01L2924/1306 , H01L2924/13091 , H01L2924/00014 , H01L2924/00012 , H01L2924/01032 , H01L2224/03 , H01L2924/00
摘要： A device and method for fabrication includes providing a first substrate assembly including a first substrate and a first metal layer formed on the first substrate and a second substrate assembly including a second substrate and a second metal layer formed on the second substrate. The first metal layer is joined to the second metal layer using a cold welding process wherein one of the first substrate and the second substrate includes a semiconductor channel layer for forming a transistor device.
摘要翻译：一种用于制造的器件和方法，包括提供包括第一衬底和形成在第一衬底上的第一金属层的第一衬底组件以及包括形成在第二衬底上的第二衬底和第二金属层的第二衬底组件。使用冷焊工艺将第一金属层接合到第二金属层，其中第一衬底和第二衬底之一包括用于形成晶体管器件的半导体沟道层。

29. 发明授权

US08809860B2 III-V compound semiconductor material passivation with crystalline interlayer 有权
标题翻译： III-V化合物半导体材料钝化与晶体中间层
公开(公告)号：US08809860B2
公开(公告)日：2014-08-19
申请号：US13775968
申请日：2013-02-25
申请人： International Business Machines Corporation
发明人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
IPC分类号： H01L29/04 , H01L29/10
CPC分类号： H01L29/0603 , H01L21/28158 , H01L21/28264 , H01L29/517 , H01L29/66522 , H01L29/78 , H01L29/7833
摘要： The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
摘要翻译：本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

30. 发明申请

US20130168834A1 III-V COMPOUND SEMICONDUCTOR MATERIAL PASSIVATION WITH CRYSTALLINE INTERLAYER 有权
标题翻译： III-V化合物半导体材料与晶体间隔层的钝化
公开(公告)号：US20130168834A1
公开(公告)日：2013-07-04
申请号：US13775968
申请日：2013-02-25
申请人： International Business Machines Corporation
发明人： Kuen-Ting Shiu , Dechao Guo , Shu-Jen Han , Edward W. Kiewra , Masaharu Kobayashi
IPC分类号： H01L29/06
CPC分类号： H01L29/0603 , H01L21/28158 , H01L21/28264 , H01L29/517 , H01L29/66522 , H01L29/78 , H01L29/7833
摘要： The present disclosure reduces and, in some instances, eliminates the density of interface states in III-V compound semiconductor materials by providing a thin crystalline interlayer onto an upper surface of a single crystal III-V compound semiconductor material layer to protect the crystallinity of the single crystal III-V compound semiconductor material layer's surface atoms prior to further processing of the structure.
摘要翻译：本公开通过在单晶III-V化合物半导体材料层的上表面上提供薄的晶体中间层来减少并且在一些情况下消除III-V族化合物半导体材料中的界面态的密度，以保护单晶III-V化合物半导体材料层的结晶度单晶III-V化合物半导体材料层的表面原子在进一步处理结构之前。

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