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1. 发明申请

US20170263702A1 SELF-FORMING SPACERS USING OXIDATION 审中-公开
公开(公告)号：US20170263702A1
公开(公告)日：2017-09-14
申请号：US15604719
申请日：2017-05-25
申请人： International Business Machines Corporation
发明人： Kevin K. Chan , Masaharu Kobayashi , Effendi Leobandung
IPC分类号： H01L29/06 , H01L21/34 , H01L29/66 , H01L29/78 , H01L21/311 , H01L21/321
CPC分类号： H01L29/0649 , H01L21/0262 , H01L21/31111 , H01L21/32105 , H01L21/34 , H01L21/38 , H01L29/66545 , H01L29/66795 , H01L29/785
摘要： A method of forming a self-forming spacer using oxidation. The self-forming spacer may include forming a fin field effect transistor on a substrate, the fin field effect transistor includes a gate on a fin, the gate is perpendicular to the fin; forming a gate spacer on the gate and a fin spacer on the fin, the gate spacer and the fin spacer are formed in a single step by oxidizing an exposed surface of the gate and an exposed surface of the fin; and removing the fin spacer from the fin.

2. 发明授权

US09299924B1 Injection pillar definition for line MRAM by a self-aligned sidewall transfer 有权
标题翻译：注射柱定义通过自对准侧壁转移线MRAM
公开(公告)号：US09299924B1
公开(公告)日：2016-03-29
申请号：US14753163
申请日：2015-06-29
申请人： International Business Machines Corporation
发明人： Anthony J. Annunziata , Joel D. Chudow , Michael C. Gaidis , Rohit Kilaru
IPC分类号： H01L43/12 , H01L21/34 , H01L43/02 , H01L43/08 , H01L27/22
CPC分类号： H01L27/222 , G11C11/161 , H01L43/02 , H01L43/08 , H01L43/12
摘要： A technique relates to an MRAM system. A conformal film covers trenches formed in an upper material. The upper material covers conductive islands in a substrate. The conformal film is selectively etched to leave sidewalls on the trenches. The sidewalls are etched into vertical columns self-aligned to and directly on top of the conductive islands below. A filling material is deposited and planarized to leave exposed tops of the vertical columns. An MTJ element is formed on top of the filling material and exposed tops of the vertical columns. The MTJ element is patterned into lines corresponding to the vertical columns, and each of the lines has a line MTJ element self-aligned to one of the vertical columns. Line MRAM devices are formed by patterning the MTJ element into the lines. Each of line MRAM devices respectively include the line MTJ element self-aligned to the one of the vertical columns.
摘要翻译：技术涉及MRAM系统。保形膜覆盖形成在上部材料中的沟槽。上部材料覆盖基板中的导电岛。选择性地蚀刻保形膜以在沟槽上留下侧壁。侧壁被蚀刻成垂直的柱，其自对准并且直接位于下面的导电岛的顶部。将填充材料沉积并平坦化以留下垂直柱的暴露顶部。 MTJ元件形成在填充材料的顶部和垂直柱的暴露的顶部。将MTJ元件图案化成对应于垂直列的线，并且每条线具有与其中一个垂直列自对准的线MTJ元件。线路MRAM器件通过将MTJ元件图案化成线。线路MRAM设备中的每一个分别包括与一个垂直列自对准的线MTJ元件。

3. 发明授权

US09006024B2 Method for manufacturing semiconductor device 有权
标题翻译：制造半导体器件的方法
公开(公告)号：US09006024B2
公开(公告)日：2015-04-14
申请号：US13865344
申请日：2013-04-18
申请人： Semiconductor Energy Laboratory Co., Ltd.
发明人： Kengo Akimoto
IPC分类号： H01L27/12 , H01L21/34 , H01L29/66 , H01L29/786 , H01L27/115 , H01L27/118
CPC分类号： H01L29/66765 , H01L27/1156 , H01L27/11807 , H01L27/1225 , H01L27/1251 , H01L27/127 , H01L29/7869
摘要： In a semiconductor device in which transistors are formed in a plurality of layers to form a stack structure, a method for manufacturing the semiconductor device formed by controlling the threshold voltage of the transistors formed in the layers selectively is provided. Further, a method for manufacturing the semiconductor device by which oxygen supplying treatment is effectively performed is provided. First oxygen supplying treatment is performed on a first oxide semiconductor film including a first channel formation region of a transistor in the lower layer. Then, an interlayer insulating film including an opening which is formed so that the first channel formation region is exposed is formed over the first oxide semiconductor film and second oxygen supplying treatment is performed on a second oxide semiconductor film including a second channel formation region over the interlayer insulating film and the exposed first channel formation region.
摘要翻译：在其中以多层形成晶体管以形成堆叠结构的半导体器件中，提供了通过选择性地控制形成在层中的晶体管的阈值电压而形成的制造半导体器件的方法。此外，提供了一种用于制造有效执行氧气供应处理的半导体器件的方法。在包括下层的晶体管的第一沟道形成区域的第一氧化物半导体膜上进行第一氧供给处理。然后，在第一氧化物半导体膜的上方形成包括形成为露出第一沟道形成区域的开口的层间绝缘膜，在第二氧化物半导体膜上进行第二氧供给处理，该第二氧化物半导体膜包括第二沟道形成区域层间绝缘膜和暴露的第一通道形成区域。

4. 发明授权

US08471252B2 Semiconductor device and method for manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US08471252B2
公开(公告)日：2013-06-25
申请号：US12535715
申请日：2009-08-05
申请人： Shunpei Yamazaki , Hidekazu Miyairi , Kengo Akimoto , Kojiro Shiraishi
发明人： Shunpei Yamazaki , Hidekazu Miyairi , Kengo Akimoto , Kojiro Shiraishi
IPC分类号： H01L21/34 , H01L29/786
CPC分类号： H01L29/66742 , H01L29/78621 , H01L29/7869
摘要： An embodiment is to include a staggered (top gate structure) thin film transistor in which an oxide semiconductor film containing In, Ga, and Zn is used as a semiconductor layer and a buffer layer is provided between the semiconductor layer and a source and drain electrode layers. A metal oxide layer having higher carrier concentration than the semiconductor layer is provided intentionally as the buffer layer between the source and drain electrode layers and the semiconductor layer, whereby an ohmic contact is formed.
摘要翻译：一个实施例是包括交错（顶栅结构）薄膜晶体管，其中使用含有In，Ga和Zn的氧化物半导体膜作为半导体层，并且缓冲层设置在半导体层与源极和漏极之间层。有意地提供具有比半导体层更高的载流子浓度的金属氧化物层作为源极和漏极电极层与半导体层之间的缓冲层，从而形成欧姆接触。

5. 发明申请

US20120319104A1 METHOD FOR PRODUCING CIRCUIT BOARD, CIRCUIT BOARD AND DISPLAY DEVICE 审中-公开
标题翻译：生产电路板，电路板和显示装置的方法
公开(公告)号：US20120319104A1
公开(公告)日：2012-12-20
申请号：US13579286
申请日：2010-11-04
申请人： Yoshihito Hara , Yukinobu Nakata
发明人： Yoshihito Hara , Yukinobu Nakata
IPC分类号： H01L29/26 , H01L21/34
CPC分类号： H01L29/7869 , H01L27/1225 , H01L27/3244 , H01L27/3262 , H01L29/78618 , H01L29/78633
摘要： Provided is a method of producing a circuit board of which the aperture ratio is increased. The method of producing a circuit board of the present invention is a method of producing a circuit board that includes a thin film transistor, the thin film transistor including an oxide semiconductor layer, the method including steps of: forming the oxide semiconductor layer; and converting the oxide semiconductor layer into a conductive form.
摘要翻译：提供一种制造开口率增加的电路板的方法。本发明的制造电路板的方法是一种制造包括薄膜晶体管的电路板的方法，该薄膜晶体管包括氧化物半导体层，该方法包括以下步骤：形成氧化物半导体层; 并将氧化物半导体层转换为导电形式。

6. 发明申请

US20120292615A1 SEMICONDUCTOR MEMORY DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体存储器件及其制造方法
公开(公告)号：US20120292615A1
公开(公告)日：2012-11-22
申请号：US13471667
申请日：2012-05-15
申请人： Toshihiko Saito
发明人： Toshihiko Saito
IPC分类号： H01L29/786 , H01L21/34
CPC分类号： H01L29/7869 , G11C11/404 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L21/84 , H01L27/1156 , H01L27/1207 , H01L27/1225
摘要： A memory cell therein includes a first transistor and a capacitor and stores data corresponding to a potential held in the capacitor. The first transistor includes a pair of electrodes, an insulating film in contact with side surfaces of the electrodes, a first gate electrode provided between the electrodes with the insulating film provided between the first gate electrode and each electrode and whose top surface is at a lower level than top surfaces of the electrodes, a first gate insulating film over the first gate electrode, an oxide semiconductor film in contact with the first gate insulating film and the electrodes, a second gate insulating film at least over the oxide semiconductor film, and a second gate electrode over the oxide semiconductor film with the second gate insulating film provided therebetween. The capacitor is connected to the first transistor through one of the electrodes.
摘要翻译：其中的存储单元包括第一晶体管和电容器，并且存储对应于保持在电容器中的电位的数据。所述第一晶体管包括一对电极，与所述电极的侧面接触的绝缘膜，设置在所述电极之间的第一栅电极，所述绝缘膜设置在所述第一栅电极与每个电极之间，并且其顶表面处于下部比第一栅极电极上的第一栅极绝缘膜，与第一栅极绝缘膜和电极接触的氧化物半导体膜，至少在氧化物半导体膜上的第二栅极绝缘膜，和第二栅极电极在氧化物半导体膜上方，其间设置有第二栅极绝缘膜。电容器通过其中一个电极连接到第一晶体管。

7. 发明申请

US20120199827A1 THIN-FILM TRANSISTOR CIRCUIT SUBSTRATE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：薄膜晶体管电路基板及其制造方法
公开(公告)号：US20120199827A1
公开(公告)日：2012-08-09
申请号：US13329545
申请日：2011-12-19
申请人： Tetsuya Shibata , Hajime Watakabe , Atsushi Sasaki , Yuki Matsuura , Muneharu Akiyoshi , Hiroyuki Watanabe
发明人： Tetsuya Shibata , Hajime Watakabe , Atsushi Sasaki , Yuki Matsuura , Muneharu Akiyoshi , Hiroyuki Watanabe
IPC分类号： H01L29/786 , H01L21/34
CPC分类号： H01L27/1225 , H01L29/66969 , H01L29/78606 , H01L29/7869
摘要： According to one embodiment, a method of manufacturing a thin-film transistor circuit substrate including forming an oxide semiconductor thin film above an insulative substrate, forming a gate insulation film and a gate electrode which are stacked on a first region of the oxide semiconductor thin film, and exposing from the gate insulation film a second region and a third region of the oxide semiconductor thin film, the second region and the third region being located on both sides of the first region of the oxide semiconductor thin film, forming an interlayer insulation film of silicon nitride including dangling bonds of silicon, the interlayer insulation film covering the second region and the third region of the oxide semiconductor thin film, the gate insulation film and the gate electrode, and forming a source electrode and a drain electrode.
摘要翻译：根据一个实施例，制造薄膜晶体管电路衬底的方法包括在绝缘衬底上形成氧化物半导体薄膜，形成栅极绝缘膜和栅电极，所述栅极绝缘膜和栅电极层叠在氧化物半导体薄膜的第一区域上并且从所述栅极绝缘膜暴露所述氧化物半导体薄膜的第二区域和第三区域，所述第二区域和所述第三区域位于所述氧化物半导体薄膜的所述第一区域的两侧，形成层间绝缘膜包括硅的悬挂键，覆盖第二区域的层间绝缘膜和氧化物半导体薄膜的第三区域，栅极绝缘膜和栅电极，以及形成源电极和漏电极。

8. 发明申请

US20120180663A1 VACUUM TRAP LABYRINTH 失效
标题翻译：真空皮带拉链
公开(公告)号：US20120180663A1
公开(公告)日：2012-07-19
申请号：US13008088
申请日：2011-01-18
申请人： Mark Charles Easton , Joseph P. DeGeorge
发明人： Mark Charles Easton , Joseph P. DeGeorge
IPC分类号： H01L21/34 , B01D45/08
CPC分类号： B01D45/08 , C23C16/4412
摘要： Embodiments of the present invention provide a vacuum trap labyrinth with improved trapping characteristics. The vacuum trap labyrinth comprised of an inner part and an outer part that fit together while in use, and come apart for easy cleaning during maintenance. The vacuum trap labyrinth is installed in a catchpot. In one embodiment, an O-ring is used to seal off an area of the catchpot to facilitate a visual inspection.
摘要翻译：本发明的实施例提供一种具有改进的捕集特性的真空阱迷宫。真空陷阱迷宫由内部和外部构成，在使用时装配在一起，并在维护期间分开以便于清洁。真空陷阱迷宫安装在收集罐中。在一个实施例中，O形环用于密封收集罐的区域以便于目视检查。

9. 发明申请

US20120138921A1 SEMICONDUCTOR DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：半导体器件及其制造方法
公开(公告)号：US20120138921A1
公开(公告)日：2012-06-07
申请号：US13299644
申请日：2011-11-18
申请人： Yuta ENDO , Kosei NODA
发明人： Yuta ENDO , Kosei NODA
IPC分类号： H01L29/22 , H01L21/336 , H01L27/06 , H01L21/34 , H01L29/20 , H01L29/16
CPC分类号： H01L27/1288 , H01L27/1225
摘要： A conductive film to be a gate electrode, a first insulating film to be a gate insulating film, a semiconductor film in which a channel region is formed, and a second insulating film to be a channel protective film are successively formed. With the use of a resist mask formed by performing light exposure with the use of a photomask which is a multi-tone mask and development, i) in a region without the resist mask, the second insulating film, the semiconductor film, the first insulating film, and the conductive film are successively etched, ii) the resist mask is made to recede by ashing or the like and only the region of the resist mask with small thickness is removed, so that part of the second insulating film is exposed, and iii) the exposed part of the second insulating film is etched, so that a pair of opening portions is formed.
摘要翻译：依次形成作为栅电极的导电膜，作为栅绝缘膜的第一绝缘膜，形成沟道区的半导体膜和作为沟道保护膜的第二绝缘膜。通过使用通过使用作为多色调掩模和显影的光掩模进行曝光而形成的抗蚀剂掩模，i）在没有抗蚀剂掩模的区域中，第二绝缘膜，半导体膜，第一绝缘体膜和导电膜依次蚀刻，ii）通过灰化等使抗蚀剂掩模后退，并且仅去除厚度小的抗蚀剂掩模的区域，使第二绝缘膜的一部分露出，并且 iii）蚀刻第二绝缘膜的暴露部分，从而形成一对开口部。

10. 发明申请

US20120097942A1 SEMICONDUCTOR DEVICE AND METHOD FOR MANUFACTURING SEMICONDUCTOR DEVICE 有权
标题翻译：半导体器件及制造半导体器件的方法
公开(公告)号：US20120097942A1
公开(公告)日：2012-04-26
申请号：US13274512
申请日：2011-10-17
申请人： Yuki Imoto , Tetsunori Maruyama , Takatsugu Omata , Yusuke Nonaka , Tatsuya Honda , Akiharu Miyanaga
发明人： Yuki Imoto , Tetsunori Maruyama , Takatsugu Omata , Yusuke Nonaka , Tatsuya Honda , Akiharu Miyanaga
IPC分类号： H01L29/786 , H01L21/34
CPC分类号： H01L29/7869 , H01L21/02554 , H01L21/02565 , H01L21/02631 , H01L29/4908
摘要： It is an object of an embodiment of the present invention to reduce leakage current between a source and a drain in a transistor including an oxide semiconductor. As a first gate film in contact with a gate insulating film, a compound conductor which includes indium and nitrogen and whose band gap is less than 2.8 eV is used. Since this compound conductor has a work function of greater than or equal to 5 eV, preferably greater than or equal to 5.5 eV, the electron concentration in an oxide semiconductor film can be maintained extremely low. As a result, the leakage current between the source and the drain is reduced.
摘要翻译：本发明的一个实施例的目的是减少包括氧化物半导体的晶体管中的源极和漏极之间的漏电流。作为与栅极绝缘膜接触的第一栅极膜，使用包含铟和氮并且其带隙小于2.8eV的复合导体。由于该复合导体具有大于或等于5eV，优选大于或等于5.5eV的功函数，所以氧化物半导体膜中的电子浓度可以保持极低。结果，源极和漏极之间的漏电流减小。

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