专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

21. 发明授权

US09349600B2 Semiconductor device manufacturing method and semiconductor device 有权
标题翻译：半导体器件制造方法和半导体器件
公开(公告)号：US09349600B2
公开(公告)日：2016-05-24
申请号：US14547859
申请日：2014-11-19
申请人： FUJITSU SEMICONDUCTOR LIMITED
发明人： Satoshi Torii , Hideaki Matsumura , Hikaru Kokura , Etsuro Kawaguchi , Katsuaki Ookoshi , Yuka Kase , Kengo Inoue
IPC分类号： H01L21/8242 , H01L31/00 , H01L21/28 , H01L29/423 , H01L29/66 , H01L27/115
CPC分类号： H01L27/1157 , H01L21/28158 , H01L21/28282 , H01L21/31116 , H01L21/76224 , H01L27/11565 , H01L27/11573 , H01L27/11575 , H01L29/4234 , H01L29/6659 , H01L29/66833 , H01L29/7833
摘要： A semiconductor device manufacturing method includes: forming an element isolation insulating film in a semiconductor substrate; forming a first film on a surface of the semiconductor substrate; forming a second film on the element isolation insulating film and on the first film; forming a first resist pattern that includes a first open above the element isolation insulating film in a first region; removing the second film on the element isolation insulating film in the first region to separate the second film in the first region into a plurality of parts by performing first etching; forming a third film on the second film in the first region; forming a first gate electrode on the third film in the first region; and forming a first insulating film that includes the first to third films under the first gate electrode by patterning the first to third films.
摘要翻译：半导体器件制造方法包括：在半导体衬底中形成元件隔离绝缘膜; 在所述半导体衬底的表面上形成第一膜; 在元件隔离绝缘膜上和第一膜上形成第二膜; 在第一区域中形成包括在所述元件隔离绝缘膜上方的第一开口的第一抗蚀剂图案; 去除第一区域中的元件隔离绝缘膜上的第二膜，以通过执行第一蚀刻将第一区域中的第二膜分离成多个部分; 在第一区域中的第二膜上形成第三膜; 在所述第一区域中的所述第三膜上形成第一栅电极; 以及通过对所述第一至第三膜进行构图来形成包括所述第一栅电极下方的所述第一至第三膜的第一绝缘膜。

22. 发明授权

US09337308B2 Semiconductor device and method for forming the same 有权
标题翻译：半导体装置及其形成方法
公开(公告)号：US09337308B2
公开(公告)日：2016-05-10
申请号：US14288167
申请日：2014-05-27
申请人： SK HYNIX INC.
发明人： Tae Su Jang , Min Soo Yoo
IPC分类号： H01L21/8242 , H01L29/66 , H01L27/108 , H01L29/78
CPC分类号： H01L29/7827 , H01L23/528 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L27/10805 , H01L27/10876 , H01L29/0688 , H01L29/456 , H01L29/66666
摘要： A semiconductor device and a method for forming the same are disclosed. The semiconductor device includes a first junction region formed at the bottom of a vertical pillar, a bit line formed below the first junction region, and an insulation film formed below the bit line. As a result, the 4F2-sized semiconductor device is provided and the bit line is configured in the form of a laminated structure of a conductive layer and a polysilicon layer, so that bit line resistance is reduced. In addition, the semiconductor device reduces ohmic contact resistance by forming silicide between the conductive layer and the polysilicon layer, and includes an insulation film at a position between the semiconductor substrate and the bit line, resulting in reduction of bit line capacitance. Therefore, the sensing margin of the semiconductor device is increased and the data retention time is also increased.
摘要翻译：公开了半导体器件及其形成方法。半导体器件包括形成在垂直柱的底部的第一结区域，形成在第一结区下方的位线，以及形成在位线下方的绝缘膜。结果，提供4F2尺寸的半导体器件，并且位线被配置为导电层和多晶硅层的叠层结构的形式，使得位线电阻降低。此外，半导体器件通过在导电层和多晶硅层之间形成硅化物来降低欧姆接触电阻，并且在半导体衬底和位线之间的位置处包括绝缘膜，导致位线电容降低。因此，半导体器件的感测裕度增加，并且数据保持时间也增加。

23. 发明授权

US09276088B1 Method for making high voltage integrated circuit devices in a fin-type process and resulting devices 有权
公开(公告)号：US09276088B1
公开(公告)日：2016-03-01
申请号：US14515070
申请日：2014-10-15
申请人： GLOBALFOUNDRIES Inc.
发明人： Jagar Singh
IPC分类号： H01L21/8242 , H01L29/66 , H01L27/088 , H01L21/762
CPC分类号： H01L27/0886 , H01L21/76224 , H01L21/823431 , H01L21/823481 , H01L29/0649 , H01L29/0684 , H01L29/0847 , H01L29/165 , H01L29/66795
摘要： Methods for making high voltage IC devices utilizing a fin-type process and resulting devices are disclosed. Embodiments include forming two pluralities of silicon fins on a substrate layer, separated by a space, wherein adjacent silicon fins are separated by a trench; forming an oxide layer on the substrate layer and filling a portion of each trench; forming two deep isolation trenches into the oxide layer and the substrate layer adjacent to the two pluralities of silicon fins; forming a graded voltage junction by implanting a dopant into the substrate layer below the two pluralities of silicon fins; forming a gate structure on the oxide layer and between the two pluralities of silicon fins; implanting a dopant into and under the two pluralities of silicon fins, forming source and drain regions; and forming an epitaxial layer onto the two pluralities of silicon fins to form merged source and drain fins.

24. 发明授权

US09265154B2 Packaging substrate and fabrication method thereof 有权
标题翻译：包装基板及其制造方法
公开(公告)号：US09265154B2
公开(公告)日：2016-02-16
申请号：US14461828
申请日：2014-08-18
申请人： Siliconware Precision Industries Co., Ltd.
发明人： Shao-Tzu Tang , Chi-Ching Ho , Ying-Chou Tsai
IPC分类号： H01L21/8242 , H05K1/18 , H05K1/11 , H05K3/10 , H01L49/02
CPC分类号： H05K1/186 , H01L23/49822 , H01L23/50 , H01L28/40 , H01L2924/0002 , H05K1/115 , H05K3/10 , H05K3/42 , H05K2201/10015 , H05K2203/0733 , H01L2924/00
摘要： A fabrication method of a packaging substrate is provided, which includes the steps of: forming first conductive portions on a carrier; sequentially forming a conductive post and an alignment layer on each of the first conductive portions; forming an encapsulant on the carrier for encapsulating the first conductive portions, the conductive posts and the alignment layers; forming a conductive via on each of the alignment layers in the encapsulant and forming second conductive portions on the conductive vias and the encapsulant; and removing the carrier. Each of the first conductive portions and the corresponding conductive post, the alignment layer and the conductive via form a conductive structure. The alignment layer has a vertical projection area larger than those of the conductive post and the conductive via to thereby reduce the size of the conductive post and the conductive via, thus increasing the wiring density and the electronic element mounting density.
摘要翻译：提供一种封装基板的制造方法，其包括以下步骤：在载体上形成第一导电部分; 在每个第一导电部分上依次形成导电柱和取向层; 在载体上形成密封剂，用于封装第一导电部分，导电柱和对准层; 在所述密封剂中的每个取向层上形成导电孔，并在所述导电通孔和所述密封剂上形成第二导电部分; 并移除载体。每个第一导电部分和相应的导电柱，对准层和导电通孔形成导电结构。取向层具有大于导电柱和导电通孔的垂直投影面积，从而减小导电柱和导电通孔的尺寸，从而增加布线密度和电子元件安装密度。

25. 发明授权

US09263453B1 Secondary use of aspect ratio trapping holes as eDRAM structure 有权
公开(公告)号：US09263453B1
公开(公告)日：2016-02-16
申请号：US14501366
申请日：2014-09-30
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Bruce B. Doris , Ali Khakifirooz , Alexander Reznicek
IPC分类号： H01L27/06 , H01L21/8242 , H01L27/108
CPC分类号： H01L29/1054 , H01L27/108 , H01L27/1082 , H01L27/10826 , H01L27/10829 , H01L27/10832 , H01L27/10858 , H01L27/10867 , H01L27/1087 , H01L27/10879 , H01L27/10894 , H01L29/20 , H01L29/78
摘要： A semiconductor structure is provided according to a method in which an aspect ratio trapping process is employed. The structure includes a semiconductor substrate comprising a first semiconductor material having a first lattice constant. A first layer of second semiconductor material formed on the substrate, the first layer having a second lattice constant that is greater than the first lattice constant. A second layer of a semi-insulating, third semiconductor material is formed atop a top surface of the first layer. A transistor device is formed on top of the second layer. An eDRAM structure is connected electronically with a channel region of the transistor device, the eDRAM structure extending from the channel region of the transistor device to a sub-surface below a top surface of the semiconductor substrate.

26. 发明授权

US09252361B2 Electronic device and method for fabricating the same 有权
标题翻译：电子器件及其制造方法
公开(公告)号：US09252361B2
公开(公告)日：2016-02-02
申请号：US14461255
申请日：2014-08-15
申请人： SK hynix Inc.
发明人： Young-Ju Lee
IPC分类号： H01L21/8242 , H01L45/00 , G06F12/08 , H01L27/24
CPC分类号： H01L27/222 , G06F12/0831 , G06F12/0866 , G06F2212/621 , G11C11/161 , H01L27/228 , H01L27/2463 , H01L43/02 , H01L43/08 , H01L43/10 , H01L43/12 , H01L45/04 , H01L45/1233 , H01L45/1675
摘要： Provided is an electronic device including a semiconductor memory. The semiconductor memory may include: an interlayer dielectric layer formed over a substrate including first and second areas; a first contact plug contacted with the substrate through the interlayer dielectric layer of the second area; an anti-peeling layer formed over the interlayer dielectric layer including the first contact plug; a second contact plug contacted with the substrate through the anti-peeling layer and the interlayer dielectric layer in the first area; and a variable resistance pattern contacted with the second contact plug.
摘要翻译：提供一种包括半导体存储器的电子设备。半导体存储器可以包括：在包括第一和第二区域的衬底上形成的层间电介质层; 第一接触插塞通过第二区域的层间介电层与基板接触; 形成在包括所述第一接触插塞的所述层间绝缘层之上的防剥离层; 第二接触插塞通过第一区域中的抗剥离层和层间绝缘层与基板接触; 以及与第二接触插塞接触的可变电阻图案。

27. 发明授权

US09209172B2 FinFET and fin-passive devices 有权
标题翻译： FinFET和鳍式无源器件
公开(公告)号：US09209172B2
公开(公告)日：2015-12-08
申请号：US14272771
申请日：2014-05-08
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Ramachandra Divakaruni , Ali Khakifirooz , Theodorus E. Standaert
IPC分类号： H01L21/8242 , H01L27/06 , H01L21/8238 , H01L21/3065 , H01L21/308 , H01L27/092 , H01L21/762 , H01L21/02 , H01L29/06 , H01L49/02 , H01L29/861 , H01L29/66
CPC分类号： H01L27/0924 , H01L21/02164 , H01L21/3065 , H01L21/308 , H01L21/3083 , H01L21/762 , H01L21/76224 , H01L21/823431 , H01L21/823821 , H01L21/823878 , H01L27/0629 , H01L27/0886 , H01L28/00 , H01L28/40 , H01L28/60 , H01L29/06 , H01L29/0649 , H01L29/0653 , H01L29/0688 , H01L29/267 , H01L29/66 , H01L29/66136 , H01L29/861 , H01L29/8613
摘要： A method of forming a semiconductor structure within a semiconductor substrate is provided. The method may include forming, on the substrate, a first group of fins associated with a first device; a second group of fins associated with a second device; and a third group of fins located between the first group of fins and the second group of fins, whereby the third group of fins are associated with a third device. A shallow trench isolation (STI) region is formed between the first and the second group of fins by recessing the third group of fins into an opening within the substrate, such that the recessed third group of fins includes a fin top surface that is located below a top surface of the substrate. The top surface of the substrate is substantially coplanar with a fin bottom surface corresponding to the first and second group of fins.
摘要翻译：提供了一种在半导体衬底内形成半导体结构的方法。该方法可以包括在衬底上形成与第一装置相关联的第一组翅片; 与第二装置相关联的第二组翅片; 以及第三组散热片，位于所述第一散热片组和所述第二组翅片之间，由此所述第三组散热片与第三装置相关联。通过将第三组翅片凹入基板内的开口中，在第一和第二组翅片之间形成浅沟槽隔离（STI）区域，使得凹陷的第三组翅片包括位于下方的翅片顶表面衬底的顶表面。基板的顶表面与对应于第一组翅片和第二组翅片的翅片底面基本共面。

28. 发明授权

US09190282B2 High-K dielectric layer based semiconductor structures and fabrication process thereof 有权
标题翻译：基于高K电介质层的半导体结构及其制造方法
公开(公告)号：US09190282B2
公开(公告)日：2015-11-17
申请号：US13662535
申请日：2012-10-28
申请人： Aileen Li , Jinghua Ni
发明人： Aileen Li , Jinghua Ni
IPC分类号： H01L21/8242 , H01L21/28 , H01L29/51 , H01L29/78
CPC分类号： H01L21/28202 , H01L29/518 , H01L29/78
摘要： A method is disclosed for fabricating a semiconductor structure. The method includes providing a semiconductor substrate, forming a first dielectric layer on a surface of the semiconductor substrate based on a first-type oxidation, and forming a high-K dielectric layer on a surface of the first dielectric layer. The method also includes performing a first thermal annealing process to remove the first dielectric layer between the semiconductor substrate and the high-K dielectric layer such that the high-K dielectric layer is on the surface of the semiconductor substrate. Further, the method includes performing a second thermal annealing process to form a second dielectric layer on the surface of the semiconductor substrate between the semiconductor substrate and the high-K dielectric layer, based on a second-type oxidation different from the first-type oxidation, such that high-K dielectric layer is on the second dielectric layer instead of the first dielectric layer.
摘要翻译：公开了制造半导体结构的方法。该方法包括提供半导体衬底，基于第一类型氧化在半导体衬底的表面上形成第一电介质层，以及在第一电介质层的表面上形成高K电介质层。该方法还包括执行第一热退火处理以去除半导体衬底和高K电介质层之间的第一介电层，使得高K电介质层在半导体衬底的表面上。此外，该方法包括进行第二热退火处理以在半导体衬底和高K电介质层之间的半导体衬底的表面上形成第二介电层，基于与第一类型氧化不同的第二类型氧化使得高K电介质层位于第二介电层上而不是第一介电层。

29. 发明授权

US09147608B2 Integrated circuit fabrication 有权
公开(公告)号：US09147608B2
公开(公告)日：2015-09-29
申请号：US14486890
申请日：2014-09-15
申请人： MICRON TECHNOLOGY, INC.
发明人： Luan C. Tran , John Lee , Zengtao Liu , Eric Freeman , Russell Nielsen
IPC分类号： H01L21/8242 , H01L21/768 , H01L21/033 , H01L21/311 , H01L23/544 , H01L27/105 , H01L21/306 , H01L21/308
CPC分类号： H01L21/0334 , H01L21/0337 , H01L21/0338 , H01L21/30604 , H01L21/3083 , H01L21/31144 , H01L21/76816 , H01L21/76877 , H01L21/76897 , H01L23/544 , H01L27/1052 , H01L2924/0002 , Y10S438/947 , H01L2924/00
摘要： A method for defining patterns in an integrated circuit comprises defining a plurality of features in a first photoresist layer using photolithography over a first region of a substrate. The method further comprises using pitch multiplication to produce at least two features in a lower masking layer for each feature in the photoresist layer. The features in the lower masking layer include looped ends. The method further comprises covering with a second photoresist layer a second region of the substrate including the looped ends in the lower masking layer. The method further comprises etching a pattern of trenches in the substrate through the features in the lower masking layer without etching in the second region. The trenches have a trench width.

30. 发明授权

US09136357B1 Fabrication process for mitigating external resistance and interface state density in a multigate device 有权
标题翻译：用于减轻多设备中外部电阻和接口状态密度的制造过程
公开(公告)号：US09136357B1
公开(公告)日：2015-09-15
申请号：US14197746
申请日：2014-03-05
申请人： International Business Machines Corporation
发明人： Anirban Basu , Guy Cohen , Amlan Majumdar
IPC分类号： H01L21/8242 , H01L21/00 , H01L21/337 , H01L21/338 , H01L29/66 , H01L21/02 , H01L29/78 , H01L29/205
CPC分类号： H01L29/205 , H01L29/66795 , H01L29/785
摘要： A method for fabricating a multigate device includes forming a fin on a substrate of the multigate device, the fin being formed of a semiconductor material, growing a first conformal epitaxial layer directly on the fin and substrate, wherein the first conformal epitaxial layer is undoped or lightly doped, growing a second conformal epitaxial layer directly on the first conformal epitaxial layer, wherein the second conformal epitaxial layer is highly doped, selectively removing a portion of the second epitaxial layer to expose a portion of the first conformal epitaxial layer and thereby form a trench, and forming a gate within the trench.
摘要翻译：一种用于制造多重装置的方法包括在多重装置的衬底上形成翅片，翅片由半导体材料形成，直接在翅片和衬底上生长第一共形外延层，其中第一共形外延层未掺杂或轻掺杂，直接在第一共形外延层上生长第二共形外延层，其中第二共形外延层是高度掺杂的，选择性地去除第二外延层的一部分以暴露第一共形外延层的一部分，从而形成沟槽，并在沟槽内形成栅极。

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式