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1. 发明授权

US10083864B2 Self aligned conductive lines with relaxed overlay 有权
公开(公告)号：US10083864B2
公开(公告)日：2018-09-25
申请号：US15405600
申请日：2017-01-13
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sean D. Burns , Lawrence A. Clevenger , Matthew E. Colburn , Sivananda K. Kanakasabapathy , Yann A. M. Mignot , Christopher J. Penny , Roger A. Quon , Nicole A. Saulnier
IPC分类号： H01L21/768 , H01L21/033
CPC分类号： H01L21/76897 , H01L21/0334 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L23/528
摘要： A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.

2. 发明授权

US09989856B2 Method of manufacturing semiconductor devices 有权
公开(公告)号：US09989856B2
公开(公告)日：2018-06-05
申请号：US15080706
申请日：2016-03-25
申请人： Samsung Electronics Co., Ltd.
发明人： Jung-Woo Seo , Sang-Jin Kim , Jong-Seo Hong , Jong-Hoon Nah , Choon-Ho Song
IPC分类号： G03F7/20 , H01L29/66 , H01L21/033 , H01L21/311 , H01L21/3213
CPC分类号： G03F7/2022 , G03F7/2002 , H01L21/0334 , H01L21/31144 , H01L21/32139 , H01L29/66545 , H01L29/66795
摘要： Disclosed is a method of manufacturing semiconductor devices. A dummy gate structure is formed on a pattern area defined by an edge area of a substrate. An interlayer insulating layer pattern is formed to cover the pattern area and exposing the edge area of the substrate. A blocking pattern is formed on the interlayer insulating layer pattern such that the edge area of the substrate is covered with the blocking pattern and the pattern area of the substrate is exposed through the blocking pattern. A gate hole in the pattern area of the substrate in correspondence to the dummy gate structure, and a metal gate structure is formed in the gate hole. Accordingly, the edge area of the substrate is protected in the etching process and the deposition process of the replacement gate metal (RGM) process.

3. 发明授权

US09972502B2 Systems and methods for performing in-situ deposition of sidewall image transfer spacers 有权
公开(公告)号：US09972502B2
公开(公告)日：2018-05-15
申请号：US14851768
申请日：2015-09-11
申请人： LAM RESEARCH CORPORATION
发明人： Jae Ho Lee , Changwoo Lee , Phil Friddle , Stefan Schmitz , Naveed Ansari , Michael Goss , Noel Sun
IPC分类号： H01L21/311 , H01L21/302 , H01L21/461 , B44C1/22 , C03C15/00 , C03C25/68 , C23F1/00 , H01L21/033 , H01L21/02 , H01L21/283 , H01J37/32 , H01L21/308 , H01L21/28
CPC分类号： H01L21/31144 , H01J37/32366 , H01J2237/334 , H01L21/02164 , H01L21/02211 , H01L21/02271 , H01L21/02274 , H01L21/0332 , H01L21/0334 , H01L21/0337 , H01L21/28132 , H01L21/28141 , H01L21/283 , H01L21/3086 , H01L21/31116
摘要： A method of performing a sidewall image transfer (SIT) process includes arranging a substrate within a substrate processing chamber, wherein the substrate includes a mandrel layer formed on the substrate and etching the mandrel layer to form a plurality of mandrels. The method further includes, without removing the substrate from within the substrate processing chamber and subsequent to etching the mandrel layer, depositing a thin spacer layer such that the thin spacer layer is formed on upper surfaces of the plurality of mandrels, sidewalls of the plurality of mandrels, and portions of the substrate between the sidewalls of the plurality of mandrels, subsequent to depositing the thin spacer layer, etching the thin spacer layer to remove the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains, and, subsequent to etching the thin spacer layer from the upper surfaces of the mandrels and the portions of the substrate between the sidewalls of the plurality of mandrels, etching the plurality of mandrels to remove the plurality of mandrels from the substrate such that only the thin spacer layer formed on the sidewalls of the plurality of mandrels remains on the substrate.

4. 发明授权

US09859281B2 Dual FIN integration for electron and hole mobility enhancement 有权
公开(公告)号：US09859281B2
公开(公告)日：2018-01-02
申请号：US15219894
申请日：2016-07-26
申请人： International Business Machines Corporation
发明人： Chia-Yu Chen , Zuoguang Liu , Miaomiao Wang , Tenko Yamashita
IPC分类号： H01L27/092 , H01L21/308 , H01L29/66 , H01L21/306 , H01L21/033 , H01L21/3065 , H01L27/088 , H01L21/8234 , H01L21/8238 , H01L29/78 , H01L29/04 , H01L29/10
CPC分类号： H01L27/0924 , H01L21/0332 , H01L21/0334 , H01L21/30604 , H01L21/3065 , H01L21/3081 , H01L21/3083 , H01L21/3085 , H01L21/3086 , H01L21/823412 , H01L21/823431 , H01L21/823807 , H01L21/823821 , H01L27/0886 , H01L27/0922 , H01L29/045 , H01L29/1033 , H01L29/6656 , H01L29/66795 , H01L29/7851 , H01L29/7853 , H01L29/7855
摘要： A technique for forming a semiconductor device is provided. Sacrificial mandrels are formed over a hardmask layer on a semiconductor layer. Spacers are formed on sidewalls of the sacrificial mandrels. The sacrificial mandrels are removed to leave the spacers. A masking process leaves exposed a first set of spacers with a second set protected. In response to the masking process, a first fin etch process forms a first set of fins in the semiconductor layer via first set of spacers. The first set of fins has a vertical sidewall profile. Another masking process leaves exposed the second set of spacers with the first set of spacers and the first set of fins protected. In response to the other masking process, a second fin etch process forms a second set of fins in semiconductor layer using the second set of spacers. The second set of fins has a trapezoidal sidewall profile.

5. 发明申请

US20170275749A1 VAPOR DEPOSITION MASK AND ORGANIC EL DISPLAY DEVICE 有权
公开(公告)号：US20170275749A1
公开(公告)日：2017-09-28
申请号：US15512107
申请日：2015-10-05
申请人： Japan Display Inc.
发明人： Toshihiro SATO , Takeshi OOKAWARA
IPC分类号： C23C14/04 , H01L51/50
CPC分类号： C23C14/042 , C23C8/04 , C23C14/24 , H01L21/0275 , H01L21/0332 , H01L21/0334 , H01L21/3086 , H01L51/0011 , H01L51/50 , H01L51/5012
摘要： The purpose is providing a vapor deposition mask with high rigidity which can evaporate a uniform thickness film. A vapor deposition mask including a mask body having a main opening, a side surface of the main opening, an upper surface intersecting the side surface, and a lower surface opposing the upper surface, a first insulator contacting the lower surface, and a second insulator contacting the upper and side surfaces, wherein the first insulator includes a first region inside the main opening, and a first opening in the first region, the second insulator includes a second region inside the main opening, and a second opening in the second region, the mask body is sandwiched between the first and second insulators, and one of the first and second insulators includes a region located inside the main opening more centrally than the other and not overlapping with the other and the mask body.

6. 发明授权

US09767244B2 Integrated circuits and methods of design and manufacture thereof 有权
公开(公告)号：US09767244B2
公开(公告)日：2017-09-19
申请号：US15093646
申请日：2016-04-07
申请人： Infineon Technologies AG
发明人： Henning Haffner , Manfred Eller , Richard Lindsay
IPC分类号： G06F17/50 , H01L21/28 , H01L21/8234 , H01L27/02 , G03F1/00 , H01L27/082 , H01L27/085 , H01L21/033 , H01L27/088 , H01L29/66 , H01L29/78
CPC分类号： G06F17/5072 , G03F1/00 , G06F2217/12 , H01L21/0334 , H01L21/28123 , H01L21/823425 , H01L21/823437 , H01L27/0207 , H01L27/082 , H01L27/085 , H01L27/088 , H01L29/6659 , H01L29/7833 , Y10T29/41
摘要： Integrated circuits and methods of manufacture and design thereof are disclosed. For example, a method of manufacturing includes using a first mask to pattern a gate material forming a plurality of first and second features. The first features form gate electrodes of the semiconductor devices, whereas the second features are dummy electrodes. Based on the location of these dummy electrodes, selected dummy electrodes are removed using a second mask. The use of the method provides greater flexibility in tailoring individual devices for different objectives.

7. 发明授权

US09711469B2 Semiconductor structure having recess and manufacturing method thereof 有权
公开(公告)号：US09711469B2
公开(公告)日：2017-07-18
申请号：US14715445
申请日：2015-05-18
申请人： XINTEC INC.
发明人： Geng-Peng Pan , Yi-Ming Chang , Chia-Sheng Lin
IPC分类号： H01L23/00 , H01L21/033 , H01L21/302 , H01L23/48 , H01L21/268 , H01L21/48 , H01L21/768
CPC分类号： H01L24/03 , H01L21/0273 , H01L21/0334 , H01L21/268 , H01L21/302 , H01L21/48 , H01L21/481 , H01L21/76898 , H01L23/481 , H01L24/05 , H01L2224/0231 , H01L2224/02371 , H01L2224/02372 , H01L2224/03831 , H01L2224/05017 , H01L2224/05024 , H01L2224/05025 , H01L2224/05557 , H01L2224/0557 , H01L2924/00014
摘要： A manufacturing method of a semiconductor structure includes the following steps. A first isolation layer is formed on a first surface of a wafer substrate. A conductive pad is formed on the first isolation layer. A hollow region through the first surface and a second surface of the wafer substrate is formed, such that the first isolation layer is exposed through the hollow region. A laser etching treatment is performed on the first isolation layer that is exposed through the hollow region, such that a first opening is formed in the first isolation layer, and a concave portion exposed through the first opening is formed in the conductive pad.

8. 发明授权

US09607886B1 Self aligned conductive lines with relaxed overlay 有权
公开(公告)号：US09607886B1
公开(公告)日：2017-03-28
申请号：US15198843
申请日：2016-06-30
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Sean D. Burns , Lawrence A. Clevenger , Matthew E. Colburn , Sivananda K. Kanakasabapathy , Yann A. M. Mignot , Christopher J. Penny , Roger A. Quon , Nicole A. Saulnier
IPC分类号： H01L21/768 , H01L23/522 , H01L23/528
CPC分类号： H01L21/76897 , H01L21/0334 , H01L21/0337 , H01L21/31144 , H01L21/76816 , H01L21/76831 , H01L23/5226 , H01L23/528
摘要： A method for forming conductive lines comprises forming a hardmask on an insulator layer, a planarizing layer on the hardmask, and a hardmask on the planarizing layer, removing exposed portions of a layer of sacrificial mandrel material to form first and second sacrificial mandrels on the hardmask, and depositing a layer of spacer material in the gap, and over exposed portions of the first and second sacrificial mandrels and the hardmask. Portions of the layer of spacer material are removed to expose the first and second sacrificial mandrels. A filler material is deposited between the first and second sacrificial mandrels. A portion of the filler material is removed to expose the first and second sacrificial mandrels. Portions of the layer of spacer material are removed to expose portions of the hardmask. A trench is formed in the insulator layer, and the trench is filled with a conductive material.

9. 发明申请

US20160358813A1 METHOD OF FORMING TRENCHES 有权
标题翻译：形成倾角的方法
公开(公告)号：US20160358813A1
公开(公告)日：2016-12-08
申请号：US14733930
申请日：2015-06-08
申请人： United Microelectronics Corp.
发明人： Harn-Jiunn Wang , Chin-Lung Lin , Yi-Hsiu Lee
IPC分类号： H01L21/768
CPC分类号： H01L21/76816 , H01L21/0334 , H01L21/3083 , H01L21/31144 , H01L21/76229
摘要： A method of forming trenches is provided. A first layer, a second layer and a third layer are formed on the substrate. A patterned third layer with a plurality of third trenches is formed. A spacer is formed on sidewalls of the third trenches, following by removing a portion of the patterned third layer between the third trenches. By using the spacer and the patterned third layer as a mask, a patterned second layer with a plurality of second trenches is formed. Next, the patterned third layer and the spacer are completely removed, and a block layer is formed on the patterned second layer, filling into the at least one second trench to separate said second trench into at least two parts. The first layer is patterned by using the patterned second layer and the block layer as a mask to form a patterned first layer with first trenches.
摘要翻译：提供了一种形成沟槽的方法。在基板上形成第一层，第二层和第三层。形成具有多个第三沟槽的图案化第三层。间隔件形成在第三沟槽的侧壁上，接着通过去除第三沟槽之间的图案化第三层的一部分。通过使用间隔物和图案化的第三层作为掩模，形成具有多个第二沟槽的图案化的第二层。接下来，完全去除图案化的第三层和间隔物，并且在图案化的第二层上形成阻挡层，填充到至少一个第二沟槽中，以将所述第二沟槽分成至少两个部分。通过使用图案化的第二层和阻挡层作为掩模来对第一层进行构图，以形成具有第一沟槽的图案化的第一层。

10. 发明授权

US09425048B2 Mechanisms for semiconductor device structure 有权
标题翻译：半导体器件结构的机理
公开(公告)号：US09425048B2
公开(公告)日：2016-08-23
申请号：US14073408
申请日：2013-11-06
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Hsin-Ying Lin , Mei-Yun Wang , Hsien-Cheng Wang , Fu-Kai Yang , Shih-Wen Liu , Audrey Hsiao-Chiu Hsu
IPC分类号： H01L21/033 , H01L29/40 , H01L29/423 , H01L29/49 , H01L29/66
CPC分类号： H01L21/28123 , H01L21/0334 , H01L21/76805 , H01L21/76897 , H01L29/402 , H01L29/42376 , H01L29/4983 , H01L29/6653 , H01L29/66545 , H01L29/6656 , H01L29/6659
摘要： Embodiments of mechanisms of a semiconductor device structure are provided. The semiconductor device structure includes a substrate and a metal gate structure formed over the substrate. The semiconductor device structure further includes a funnel shaped hard mask structure formed over the metal gate structure. Formation of voids, which tend to be formed in a rectangular hard mask structure, is prevented. In addition, formation of a self-aligned contact in the semiconductor device becomes easier, and risks of shortage between the contact and a metal gate structure in the semiconductor device decreased. In addition, a method for forming the semiconductor device structure is also provided. The method may include a gate last process.
摘要翻译：提供半导体器件结构的机构的实施例。半导体器件结构包括在衬底上形成的衬底和金属栅极结构。半导体器件结构还包括形成在金属栅极结构上的漏斗形硬掩模结构。容易形成矩形硬掩模结构的空隙的形成被防止。此外，半导体器件中的自对准接触的形成变得容易，并且半导体器件中的接触和金属栅极结构之间的短缺的风险降低。此外，还提供了一种用于形成半导体器件结构的方法。该方法可以包括门最后进程。

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