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31. 发明授权

US10355674B2 Clock gating circuit 有权
公开(公告)号：US10355674B2
公开(公告)日：2019-07-16
申请号：US15658214
申请日：2017-07-24
申请人： ARM Limited
发明人： Anil Kumar Baratam , Nruthya Nagesh Prabhu , Yves Thomas Laplanche
IPC分类号： H03K3/356 , H03K17/687
摘要： Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first stage that receives an enable signal and an input clock signal and provides a first intermediate signal based on the enable signal and the input clock signal. The integrated circuit may include a second stage that receives the first intermediate signal and the input clock signal and provides a second intermediate signal based on a ternary logic response to the first intermediate signal and the input clock signal. The integrated circuit may include a third stage that receives the second intermediate signal and the input clock signal and provides an output clock signal based on the second intermediate signal and the input clock signal.

32. 发明授权

US10340917B2 Receiver circuitry and method for converting an input signal from a source voltage domain into an output signal for a destination voltage domain 有权
公开(公告)号：US10340917B2
公开(公告)日：2019-07-02
申请号：US15823481
申请日：2017-11-27
申请人： ARM Limited
发明人： Ranabir Dey , Vijaya Kumar Vinukonda , Mikael Rien
IPC分类号： H03K19/185 , H03K19/0185
摘要： The present invention provides a receiver circuit and method for receiving an input signal from a source voltage domain and converting the input signal into an output signal for a destination voltage domain. The source voltage domain operates from a supply voltage that exceeds a stressing threshold of components within the receiver circuitry, and the receiver circuitry is configured to operate from the supply voltage of the source voltage domain. The receiver circuitry comprises first internal signal generation circuitry configured to convert the input signal into a first internal signal in a first voltage range, and second internal signal generation circuitry configured to convert the input signal into a second internal signal in a second voltage range. Signal evaluation circuitry establishes a logic high voltage threshold and a logic low voltage threshold dependent on the supply voltage, and employs the first and second internal signals in order to detect based on the logic high voltage threshold and logic low voltage threshold when the input signal transitions between a logic low level and a logic high level (in either direction). Output generation circuitry then generates the output signal in dependence on the detection performed by the signal evaluation circuitry. The first voltage range and the second voltage range are such that the first internal signal and second internal signal will not exceed the stressing threshold of components in the signal evaluation circuitry. The receiver circuitry is able to reliably detect transitions in the input signal in situations where the supply voltage of the source voltage domain exceeds the stressing threshold of the receiver's components, but without overstress of the receiver's components.

33. 发明授权

US10316639B2 System and method for analyzing wellbore survey data to determine tortuosity of the wellbore using displacements of the wellbore path from reference lines 有权
公开(公告)号：US10316639B2
公开(公告)日：2019-06-11
申请号：US14612162
申请日：2015-02-02
申请人： GYRODATA, INCORPORATED
发明人： Jon Bang , Onyemelem Jegbefume , Adrian Guillermo Ledroz , John Lionel Weston
IPC分类号： G06F11/30 , E21B47/00 , E21B47/024 , E21B47/12 , E21B47/022 , G01V1/40 , G01V3/18
摘要： A system and method for providing information regarding the tortuosity of a wellbore path is provided. The method includes receiving data from a plurality of survey stations of a wellbore survey. The method further includes defining a plurality of reference lines for the wellbore path. The method further includes determining a plurality of displacements of the wellbore path from the plurality of reference lines.

34. 发明授权

US10222418B2 Scan cell for dual port memory applications 有权
公开(公告)号：US10222418B2
公开(公告)日：2019-03-05
申请号：US15368480
申请日：2016-12-02
申请人： ARM Limited
发明人： Yew Keong Chong , Teresa Louise Mclaurin , Richard Slobodnik , Frank David Frederick , Kartikey Jani
IPC分类号： G01R31/317 , G01R31/3177 , G01R31/3185 , G11C29/32
摘要： Various implementations described herein are directed to a scan cell. The scan cell may include an input phase having multiple multiplexers and a latch arranged to receive a scan input signal, a first address signal, and a second address signal and provide the scan input signal, the first address signal, or the second address signal based on a scan enable signal, a first clock signal, and a selection enable signal. The scan cell may include an output phase having multiple latches arranged to receive the scan input signal, the first address signal, or the second address signal from the input phase and provide the scan input signal, the first address signal, or the second address signal as a scan output signal based on a second clock signal and a third clock signal.

35. 发明授权

US10210303B2 Sleep signal stitching technique 有权
公开(公告)号：US10210303B2
公开(公告)日：2019-02-19
申请号：US15418613
申请日：2017-01-27
申请人： ARM Limited
发明人： Ravindra Narayana Rao , Marlin Wayne Frederick, Jr. , Karen Lee Delk , Stefan Charles Creaser
IPC分类号： G06F17/50
摘要： Various implementations described herein are directed to an apparatus having a receiver module that receives a floorplan of an integrated circuit having power gates, an obstruction, and a control pin for providing a sleep signal. The apparatus can include an identifier module that identifies where the obstruction interrupts a sequence of the power gates, organizes the sequence of the power gates into a column, and divides the column into segments in which a first segment lies below the obstruction, a second segment lies above the obstruction, and a third segment is offset from the first segment and the second segment. The apparatus can include a stitcher module that performs a sleep signal stitching for the integrated circuit by distributing the sleep signal from the control pin to the power gates that include each power gate in each of the first segment, the second segment, and the third segment.

36. 发明授权

US10199094B2 Write operation scheme for SRAM 有权
公开(公告)号：US10199094B2
公开(公告)日：2019-02-05
申请号：US15619332
申请日：2017-06-09
申请人： ARM Limited
发明人： Ankur Goel , Saikat Kumar Banik , Lokesh Kumar Saini , Vivek Asthana
IPC分类号： G11C11/412 , G11C11/419 , H01L23/528 , H01L27/11 , G11C11/418
摘要： A circuit includes a memory cell with a bitline. A pulldown nMOSFET has a gate terminal connected to an output port of a logic gate, and a drain terminal connected to the first bitline. A write select line is connected to a second input port of the logic gate. A pullup pMOSFET has a gate terminal connected to the write select line, and a drain terminal connected to the bitline.

37. 发明授权

US10199092B2 Boost circuit for memory 有权
公开(公告)号：US10199092B2
公开(公告)日：2019-02-05
申请号：US15188873
申请日：2016-06-21
申请人： ARM Limited
发明人： Mohit Chanana , Ankur Goel
IPC分类号： G11C11/00 , G11C11/419
摘要： Various implementations described herein are directed to a device having a memory cell coupled to complementary bitlines. The memory cell may store at least one data bit value associated with complementary bitline signals received via the complementary bitlines. The device may include a pair of write drivers coupled to the memory cell via the complementary bitlines. The pair of write drivers may be arranged to provide the complementary bitline signals to the memory cell based on complementary boost signals. The device may include a pair of complementary boost generators coupled to corresponding gates of the pair of write drivers. The pair of complementary boost generators may be arranged to selectively provide the complementary boost signals to the corresponding gates of the pair of write drivers based on the at least one data bit value.

38. 发明授权

US10181788B2 Rational conversion ratio converter 有权
公开(公告)号：US10181788B2
公开(公告)日：2019-01-15
申请号：US15011242
申请日：2016-01-29
申请人： The Regents of the University of Michigan
发明人： Wanyeong Jung , Dennis Michael Chen Sylvester , David Theodore Blaauw
IPC分类号： H02M3/07 , H02M1/00
摘要： Various implementations described herein are directed to an integrated circuit. The integrated circuit may include a first voltage source providing a first voltage having a first polarity. The integrated circuit may include a second voltage source providing a second voltage having a second polarity that is opposite the first polarity. The integrated circuit may include a first circuit portion configured to receive the first and second voltages and provide one or more feedback voltages. The integrated circuit may include a second circuit portion configured to receive the first and second voltages along with the one or more feedback voltages and provide an output voltage that is proportional to the first voltage based on a rational conversion ratio that is derived by selection of at least one of the first and second voltages and the one or more feedback voltages.

39. 发明授权

US10154411B2 Proximity authentication protocol 有权
公开(公告)号：US10154411B2
公开(公告)日：2018-12-11
申请号：US15447729
申请日：2017-03-02
申请人： ARM IP Limited
发明人： Brendan James Moran , Milosch Meriac , Geraint David Luff
IPC分类号： H04M1/66 , H04W12/06 , H04W4/02 , H04W12/04 , H04L29/06 , H04W4/70 , H04W4/80
摘要： A machine implemented method of authenticating a communication channel between a first device and a second device by providing proof of proximity between both devices, the method comprising: generating, at the first device, an acoustic authentication signal to be received at the second device via a solid body acoustic coupling established between the first device and the second device thereby providing proof of proximity between both devices and so authenticating the communication channel between the first device and the second device.

40. 发明授权

US10147482B2 Skewed corner tracking for memory write operations 有权
公开(公告)号：US10147482B2
公开(公告)日：2018-12-04
申请号：US15462549
申请日：2017-03-17
申请人： ARM Limited
发明人： Jitendra Dasani , Vivek Nautiyal , Shri Sagar Dwivedi , Fakhruddin Ali Bohra
IPC分类号： G11C11/419 , G11C11/418
摘要： A memory device includes a bitcell array having a plurality of bitcells, a dummy wordline, a dummy row cell pulldown, and a write tracker coupling the dummy wordline to the dummy row cell pulldown. The write tracker is configured as a transmission gate during a read operation on the bitcell array, and is configured as having only one or more active nMOSFETs during a write operation on the bitcell array.

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