专利快速检索-快速检索全球专利，免费商用专利数据库-IPRDB

1. 发明授权

US11614421B2 BioFET system 有权
公开(公告)号：US11614421B2
公开(公告)日：2023-03-28
申请号：US16869753
申请日：2020-05-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Jie Huang , Jui-Cheng Huang
IPC分类号： G01N27/41 , G01N27/414 , H03K19/185
摘要： A bio-field effect transistor (bioFET) system includes a bioFET configured to receive a first voltage signal and output a current signal. A logarithmic current-to-time converter is connected to the bioFET and is configured to receive the current signal and convert the current signal to a time domain signal. The time domain signal varies logarithmically with respect to the current signal, such that the time domain signal varies linearly with respect to the first voltage signal.

2. 发明授权

US11277137B1 Majority logic gate with non-linear input capacitors 有权
公开(公告)号：US11277137B1
公开(公告)日：2022-03-15
申请号：US17327614
申请日：2021-05-21
申请人： Kepler Computing Inc.
发明人： Sasikanth Manipatruni , Rafael Rios , Neal Reynolds , Ikenna Odinaka , Robert Menezes , Rajeev Kumar Dokania , Ramamoorthy Ramesh , Amrita Mathuriya
IPC分类号： H03K19/23 , H03K19/21 , H03K19/185 , H03K19/0185 , H03K19/17784
摘要： A new class of logic gates are presented that use non-linear polar material. The logic gates include multi-input majority gates. Input signals in the form of digital signals are driven to non-linear input capacitors on their respective first terminals. The second terminals of the non-linear input capacitors are coupled a summing node which provides a majority function of the inputs. The majority node is then coupled driver circuitry which can be any suitable logic gate such as a buffer, inverter, NAND gate, NOR gate, etc. In the multi-input majority or minority gates, the non-linear charge response from the non-linear input capacitors results in output voltages close to or at rail-to-rail voltage levels. Bringing the majority output close to rail-to-rail voltage eliminates the high leakage problem faced from majority gates formed using linear input capacitors.

3. 发明申请

US20210349053A1 BioFET SYSTEM 有权
公开(公告)号：US20210349053A1
公开(公告)日：2021-11-11
申请号：US16869753
申请日：2020-05-08
申请人： Taiwan Semiconductor Manufacturing Company, Ltd.
发明人： Yu-Jie Huang , Jui-Cheng Huang
IPC分类号： G01N27/414 , H03K19/185
摘要： A bio-field effect transistor (bioFET) system includes a bioFET configured to receive a first voltage signal and output a current signal. A logarithmic current-to-time converter is connected to the bioFET and is configured to receive the current signal and convert the current signal to a time domain signal. The time domain signal varies logarithmically with respect to the current signal, such that the time domain signal varies linearly with respect to the first voltage signal.

4. 发明申请

US20200211608A1 PERPENDICULAR MAGNETOELECTRIC SPIN ORBIT LOGIC 审中-公开
公开(公告)号：US20200211608A1
公开(公告)日：2020-07-02
申请号：US16349575
申请日：2016-12-13
申请人： Intel Corporation
发明人： Sasikanth Manipatruni , Dmitri E. Nikonov , Ian A. Young
IPC分类号： G11C11/16 , H01L27/22 , H01L43/10 , H01L43/14 , H03K19/18 , H03K19/185
摘要： An apparatus is provided which comprises: a first magnet with perpendicular magnetic anisotropy (PMA); a stack of layers, a portion of which is adjacent to the first magnet, wherein the stack of layers is to provide an inverse Rashba-Bychkov effect; a second magnet with PMA; a magnetoelectric layer adjacent to the second magnet; and a conductor coupled to at least a portion of the stack of layers and the magnetoelectric layer.

5. 发明授权

US09979393B2 Low power consumption logic cell 有权
公开(公告)号：US09979393B2
公开(公告)日：2018-05-22
申请号：US15381477
申请日：2016-12-16
申请人： Commissariat à l'Énergie Atomique et aux Énergies Alternatives
发明人： Hervé Fanet , Samer Houri , Gaël Pillonnet
IPC分类号： H03K19/00 , H03K19/185 , H03K19/02
CPC分类号： H03K19/0008 , H03K19/0013 , H03K19/0019 , H03K19/02 , H03K19/185 , H03K19/20
摘要： The invention relates to a logic cell for an integrated circuit including at least one first variable-capacitance capacitor having first and second main electrodes separated by an insulating region, and a third control electrode capable of receiving a control voltage referenced to a reference node of the cell to vary the capacitance between the first and second main electrodes, the third electrode being coupled to a node of application of a first logic input signal of the cell, and the first and second electrodes being respectively coupled to a node of application of a cell power supply voltage and to a node for supplying a logic output signal of the cell.

6. 发明申请

US20110309858A1 NON-VOLATILE LOGIC CIRCUIT AND A METHOD FOR OPERATING THE SAME 有权
标题翻译：非挥发性逻辑电路及其操作方法
公开(公告)号：US20110309858A1
公开(公告)日：2011-12-22
申请号：US13220222
申请日：2011-08-29
申请人： Yukihiro KANEKO
发明人： Yukihiro KANEKO
IPC分类号： H03K19/185
CPC分类号： H01L27/10 , G11C11/22 , H01L27/101 , H01L27/11502
摘要： In a non-volatile logic circuit, a first input electrode and a second input electrode are formed on a semiconductor layer and interposed between an electric current source electrode and an output electrode in a plan view. The first input electrode is next to the second input electrode along the a direction orthogonal to the direction between the electric current source electrode and the output electrode. A method of operating the non-volatile logic circuit includes a step of writing one state selected from four states by applying voltages to the first input electrode and the second input electrode, respectively, and a step of measuring current generated by applying the voltage between the electric current power electrode and the output electrode to determine on the basis of the current, which of the high or low resistant state the non-volatile logic circuit has.
摘要翻译：在非易失性逻辑电路中，第一输入电极和第二输入电极形成在半导体层上并且在平面图中介于电流源电极和输出电极之间。第一输入电极沿着与电流源电极和输出电极之间的方向正交的方向与第二输入电极相邻。一种操作非易失性逻辑电路的方法包括分别通过向第一输入电极和第二输入电极施加电压来写入从四种状态中选出的一种状态的步骤，以及测量通过施加电压而产生的电流的步骤电流功率电极和输出电极根据电流来确定非易失性逻辑电路具有哪些高或低电阻状态。

7. 发明授权

US06946893B2 Level shift circuit and semiconductor integrated circuit 失效
标题翻译：电平移位电路和半导体集成电路
公开(公告)号：US06946893B2
公开(公告)日：2005-09-20
申请号：US10872539
申请日：2004-06-22
申请人： Hirokatsu Hayashi , Toshiro Takahashi
发明人： Hirokatsu Hayashi , Toshiro Takahashi
IPC分类号： H01L21/822 , H01L21/8238 , H01L27/04 , H01L27/092 , H03K19/003 , H03K19/0175 , H03K19/0185 , H03K19/185
CPC分类号： H03K19/00323
摘要： A level conversion circuit is composed of a level shift circuit for supplying a level-converted signal in the same phase as the input signal and a signal in the reverse phase thereto and a follow-up circuit responsive to the earlier of the output signals of the level shift circuit for generating an output signal, wherein the follow-up circuit consists of an inverter circuit in which two p-channel type MOS transistors and two n-channel type MOS transistors are connected in series between a first voltage terminal and a second voltage terminal, of which one pair is used as input transistors and the remaining pair of transistors are subjected to feedback based on the output signal of the level shift circuit to be quickly responsive to the next variation.
摘要翻译：电平转换电路由电平移位电路构成，电平移位电路用于提供与输入信号相同相位的电平转换信号和与其相反的信号，以及响应于较早的输出信号的后续电路电平移位电路，用于产生输出信号，其中后续电路由反相电路组成，其中两个p沟道型MOS晶体管和两个n沟道型MOS晶体管串联连接在第一电压端和第二电压之间端子，其中一对用作输入晶体管，并且剩余的一对晶体管基于电平移位电路的输出信号进行反馈，以快速响应下一个变化。

8. 发明授权

US3179926A Ferroelectric logic circuits 失效
标题翻译：铁电逻辑电路
公开(公告)号：US3179926A
公开(公告)日：1965-04-20
申请号：US5883860
申请日：1960-09-27
申请人： BELL TELEPHONE LABOR INC
发明人： WOLFE ROBERT M
IPC分类号： H03K19/185
CPC分类号： H03K19/185

9. 发明授权

US3037196A Logical circuit element 失效
标题翻译：逻辑电路元件
公开(公告)号：US3037196A
公开(公告)日：1962-05-29
申请号：US59670756
申请日：1956-07-09
申请人： IBM
发明人： BRENNEMANN ANDREW E
IPC分类号： H03K3/45 , H03K19/02 , H03K19/185
CPC分类号： H03K19/02 , H03K3/45 , H03K19/185

10. 发明授权

US11303280B1 Ferroelectric or paraelectric based sequential circuit 有权
公开(公告)号：US11303280B1
公开(公告)日：2022-04-12
申请号：US17407031
申请日：2021-08-19
申请人： Kepler Computing Inc.
发明人： Amrita Mathuriya , Ikenna Odinaka , Rajeev Kumar Dokania , Rafael Rios , Sasikanth Manipatruni
IPC分类号： H03K19/23 , H03K19/185 , H03K19/17736 , H01L49/02 , G11C7/10
摘要： A low power sequential circuit (e.g., latch) uses a non-linear polar capacitor to retain charge with fewer transistors than traditional CMOS sequential circuits. In one example, a sequential circuit includes pass-gates and inverters, but without a feedback mechanism or memory element. In another example, a sequential uses load capacitors (e.g., capacitors coupled to a storage node and a reference supply). The load capacitors are implemented using ferroelectric material, paraelectric material, or linear dielectric. In one example, a sequential uses minority, majority, or threshold gates with ferroelectric or paraelectric capacitors. In one example, a sequential circuit uses minority, majority, or threshold gates configured as NAND gates.

你已经成功收藏专利！

检索式保存成功!

IPRDB

热门服务

关于我们

友情链接

联系方式