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31. 发明授权

US09666717B2 Split well zero threshold voltage field effect transistor for integrated circuits 有权
公开(公告)号：US09666717B2
公开(公告)日：2017-05-30
申请号：US14217691
申请日：2014-03-18
申请人： GLOBALFOUNDRIES Inc.
发明人： Jagar Singh , Konstantin G. Korablev , Andy Chih-Hung Wei
IPC分类号： H01L29/40 , H01L29/78 , H01L29/417 , H01L29/66 , H01L29/36 , H01L21/265
CPC分类号： H01L29/7851 , H01L21/26586 , H01L29/1041 , H01L29/105 , H01L29/36 , H01L29/41783 , H01L29/41791 , H01L29/66795
摘要： Approaches for altering the threshold voltage (e.g., to zero threshold voltage) in a fin-type field effect transistor (FinFET) device are provided. In embodiments of the invention, a first N+ region and a second N+ region are formed on a finned substrate that has a p-well construction. A region of the finned substrate located between the first N+ region and the second N+ region is doped with a negative implant species to form an n-well. The size and/or composition of this n-well region can be adjusted in view of the existing p-well construction of the substrate device to change the threshold voltage of the FinFET device (e.g., to yield a zero threshold voltage FinFET device).

32. 发明授权

US09601187B1 Method, apparatus, and system for global healing of stability-limited die through bias temperature instability 有权
公开(公告)号：US09601187B1
公开(公告)日：2017-03-21
申请号：US15046983
申请日：2016-02-18
申请人： GLOBALFOUNDRIES INC.
发明人： Akhilesh Gautam , Randy W. Mann , William McMahon , Yoann Mamy Randriamihaja , Yuncheng Song
IPC分类号： G11C11/00 , G11C11/419 , G11C7/06
CPC分类号： G11C29/56 , G11C7/04 , G11C8/08 , G11C11/418
摘要： We disclose methods, apparatus, and systems for improving semiconductor device yield and/or reliability through bias temperature instability (BTI). One device may comprise a plurality of cells of an array, wherein each of the cells comprises a pass gate and a latch; a plurality of word lines, wherein each word line controls access to each pass gate of a first number of cells; a word line driver electrically connected to each word line; and a control line configured to provide an operational write voltage or a first write voltage to each word line through the word line driver. By virtue of BTI, application of the first write voltage may lead to improved stability of data desired to be read from one or more cells of the device.

33. 发明授权

US09582629B2 Methods of generating circuit layouts using self-alligned double patterning (SADP) techniques 有权
标题翻译：使用自偏转双重图案（SADP）技术生成电路布局的方法
公开(公告)号：US09582629B2
公开(公告)日：2017-02-28
申请号：US14245868
申请日：2014-04-04
申请人： GLOBALFOUNDRIES Inc.
发明人： Lei Yuan , Li Yang , Jongwook Kye
IPC分类号： H01L21/76 , G06F17/50
CPC分类号： G06F17/5072 , G06F17/5077
摘要： At least one method disclosed herein involves creating an overall pattern layout for an integrated circuit that is to be manufactured using a self-aligned double patterning (SADP) process, forming a first metal feature having a first width on a first track of a metal layer using the SADP process, forming a second metal feature having a second width on a second track of the metal layer. The second track is adjacent to the first track. The method also includes forming an electrical connection between the first metal feature and the second metal feature to provide an effectively single metal pattern having a third width that is the sum of the first and second widths, rendering the first and second features decomposable using the SADP process; and decomposing the overall pattern layout with the first and second metal features into a mandrel mask pattern and a block mask pattern.
摘要翻译：本文公开的至少一种方法涉及为使用自对准双图案（SADP）工艺制造的集成电路的整体图案布局，在金属层的第一轨道上形成具有第一宽度的第一金属特征使用SADP工艺，在金属层的第二轨道上形成具有第二宽度的第二金属特征。第二条轨道与第一条轨道相邻。该方法还包括在第一金属特征和第二金属特征之间形成电连接，以提供具有第三宽度的有效单个金属图案，该第三宽度是第一宽度和第二宽度之和，使得第一和第二特征可以使用SADP分解处理; 并且将具有第一和第二金属特征的整体图案布局分解成心轴掩模图案和块掩模图案。

34. 发明授权

US09579506B2 Contingent cardio-protection for epilepsy patients 有权
公开(公告)号：US09579506B2
公开(公告)日：2017-02-28
申请号：US14050173
申请日：2013-10-09
申请人： Flint Hills Scientific, L.L.C.
发明人： Ivan Osorio
IPC分类号： A61N1/36 , A61N1/05
CPC分类号： A61N1/36064 , A61N1/0556 , A61N1/36053 , A61N1/36114 , A61N1/36117 , A61N1/36139 , A61N1/36185
摘要： Disclosed are methods and systems for treating epilepsy by stimulating a main trunk of a vagus nerve, or a left vagus nerve, when the patient has had no seizure or a seizure that is not characterized by cardiac changes such as an increase in heart rate, and stimulating a cardiac branch of a vagus nerve, or a right vagus nerve, when the patient has had a seizure characterized by cardiac changes such as a heart rate increase.

35. 发明授权

US09547741B2 Methods, apparatus, and system for using filler cells in design of integrated circuit devices 有权
标题翻译：在集成电路器件设计中使用填充电池的方法，装置和系统
公开(公告)号：US09547741B2
公开(公告)日：2017-01-17
申请号：US14518939
申请日：2014-10-20
申请人： GLOBALFOUNDRIES INC.
发明人： Uwe Paul Schroeder , Sushama Davar
IPC分类号： G06F17/50 , H01L29/06 , H01L29/66
CPC分类号： G06F17/5072 , G06F17/5068 , G06F17/5077 , G06F17/5081 , G06F2217/02 , G06F2217/06 , H01L29/0661 , H01L29/6681
摘要： At least one method, apparatus and system disclosed involves circuit layout for an integrated circuit device. A design for an integrated circuit device is received; The design comprises a first functional cell and a second functional cell. The first functional cell is placed on a circuit layout. A determination is made as to whether the first cell comprises a vertical boundary that is electrically floating. A filler cell is placed adjacent to the vertical boundary on the circuit layout in response to determining that the first cell comprises the vertical boundary that is electrically floating. The second functional cell is placed adjacent to the filler cell to form a contiguous active area on the circuit layout.
摘要翻译：所公开的至少一种方法，装置和系统涉及用于集成电路装置的电路布局。接收集成电路装置的设计; 该设计包括第一功能单元和第二功能单元。第一个功能单元放置在电路布局上。确定第一单元是否包括电浮动的垂直边界。响应于确定第一单元包括电浮动的垂直边界，填充单元被放置在电路布局上的垂直边界附近。第二功能单元被放置成与填充单元相邻以在电路布局上形成连续的有效区域。

36. 发明授权

US09538951B2 Detecting, assessing and managing epilepsy using a multi-variate, metric-based classification analysis 有权
标题翻译：使用多变量，基于度量的分类分析来检测，评估和管理癫痫
公开(公告)号：US09538951B2
公开(公告)日：2017-01-10
申请号：US14936492
申请日：2015-11-09
申请人： Flint Hills Scientific, L.L.C.
发明人： Ivan Osorio
IPC分类号： A61B5/00 , A61B5/024 , A61B5/04 , A61B5/0452 , A61N1/36 , A61B5/0476 , A61M16/10 , A61B5/042 , A61B5/145 , A61B5/0205 , A61B5/11 , A61B5/08 , A61B5/021 , A61B5/026 , A61B5/0488
CPC分类号： A61B5/4094 , A61B5/0205 , A61B5/02055 , A61B5/021 , A61B5/024 , A61B5/02405 , A61B5/026 , A61B5/04012 , A61B5/042 , A61B5/0452 , A61B5/0476 , A61B5/0488 , A61B5/08 , A61B5/11 , A61B5/1117 , A61B5/1118 , A61B5/14503 , A61B5/14539 , A61B5/14542 , A61B5/4836 , A61B5/4848 , A61B5/486 , A61B5/686 , A61B5/7246 , A61B5/7264 , A61B5/7267 , A61B5/7275 , A61B5/7282 , A61B5/742 , A61B5/743 , A61B5/746 , A61B2560/0242 , A61B2560/0475 , A61M16/1005 , A61M2202/0208 , A61M2205/3303 , A61N1/36064 , A61N1/36135 , G06F19/00
摘要： A method for identifying changes in an epilepsy patient's disease state, comprising: receiving at least one body data stream; determining at least one body index from the at least one body data stream; detecting a plurality of seizure events from the at least one body index; determining at least one seizure metric value for each seizure event; performing a first classification analysis of the plurality of seizure events from the at least one seizure metric value; detecting at least one additional seizure event from the at least one determined index; determining at least one seizure metric value for each additional seizure event, performing a second classification analysis of the plurality of seizure events and the at least one additional seizure event based upon the at least one seizure metric value; comparing the results of the first classification analysis and the second classification analysis; and performing a further action.
摘要翻译：一种用于识别癫痫患者疾病状态变化的方法，包括：接收至少一个身体数据流; 从所述至少一个主体数据流确定至少一个身体索引; 从所述至少一个身体指数中检测多个发作事件; 确定每个发作事件的至少一个发作度量值; 对所述多个发作事件从所述至少一个发作度量值进行第一分类分析; 从所述至少一个确定的索引中检测至少一个附加的发作事件; 确定每个附加发作事件的至少一个发作度量值，基于所述至少一个发作度量值执行所述多个发作事件和所述至少一个附加发作事件的第二分类分析; 比较第一次分类分析和第二次分类分析的结果; 并执行进一步的动作。

37. 发明授权

US09506874B2 Infrared-based metrology for detection of stress and defects around through silicon vias 有权
公开(公告)号：US09506874B2
公开(公告)日：2016-11-29
申请号：US14691392
申请日：2015-04-20
申请人： GLOBALFOUNDRIES Inc.
发明人： Ming Lei
IPC分类号： G01J3/00 , G01N21/95 , G01N21/88 , G01N21/956 , G01B11/16
CPC分类号： G01N21/9505 , G01B11/161 , G01N21/8806 , G01N21/95692 , G01N2201/061 , G01N2201/0668 , G01N2201/12
摘要： An approach for IR-based metrology for detecting stress and/or defects around TSVs of semiconductor devices is provided. Specifically, in a typical embodiment, a beam of IR light will be emitted from an IR light source through the material around the TSV. Once the beam of IR light has passed through the material around the TSV, the beam will be analyzed using one or more algorithms to determine information about TSV stress and/or defects such as imbedded cracking, etc. In one embodiment, the beam of IR light may be split into a first portion and a second portion. The first portion will be passed through the material around the TSV while the second portion is routed around the TSV. After the first portion has passed through the material around the TSV, the two portions may then be recombined, and the resulting beam may be analyzed as indicated above.

38. 发明授权

US09478506B2 Multilayer pattern transfer for chemical guides 有权
标题翻译：化学导轨的多层图案转移
公开(公告)号：US09478506B2
公开(公告)日：2016-10-25
申请号：US13787090
申请日：2013-03-06
申请人： GLOBALFOUNDRIES Inc.
发明人： Richard A. Farrell , Gerard M. Schmid , Sudharshanan Raghunathan
IPC分类号： H01L21/311 , H01L23/00 , H01L21/308 , H01L21/683 , H01L21/768 , H01L21/67
CPC分类号： H01L23/564 , H01L21/3086 , H01L21/311 , H01L21/31144 , H01L21/67109 , H01L21/6831 , H01L21/76807 , H01L2924/0002 , H01L2924/00
摘要： Approaches for multilayer pattern transfer for chemical guides are provided. In a typical embodiment, a device is formed by forming an etch mask layer (e.g., a nitride layer and an oxide layer) over a substrate (e.g., silicon (Si)). An orientation control layer (e.g., a neutral layer) is then formed over the etch mask layer, and an ARC layer (e.g., SiARC) is formed over the orientation control layer. In other embodiments, an organic planarization layer (OPL) and/or a protection layer may also be formed between the ARC layer and the orientation control layer. Regardless, a tapered etch profile/pattern may then be formed through the ARC and/or other layers.
摘要翻译：提供了用于化学导轨的多层图案转印的方法。在典型的实施例中，通过在衬底（例如，硅（Si））上形成蚀刻掩模层（例如，氮化物层和氧化物层）来形成器件。然后在蚀刻掩模层上形成取向控制层（例如中性层），并且在取向控制层上形成ARC层（例如SiARC）。在其它实施例中，也可以在ARC层和取向控制层之间形成有机平坦化层（OPL）和/或保护层。无论如何，可以通过ARC和/或其他层形成锥形蚀刻轮廓/图案。

39. 发明授权

US09451894B2 Detecting or validating a detection of a state change from a template of heart rate derivative shape or heart beat wave complex 有权
公开(公告)号：US09451894B2
公开(公告)日：2016-09-27
申请号：US14583099
申请日：2014-12-25
申请人： Flint Hills Scientific, L.L.C.
发明人： Ivan Osorio , Mark G. Frei
IPC分类号： A61B5/0452 , A61B5/04 , A61B5/024 , A61B5/00 , A61B5/0468 , A61B5/0456 , A61N1/36
CPC分类号： A61B5/4094 , A61B5/02405 , A61B5/0245 , A61B5/04012 , A61B5/04014 , A61B5/0452 , A61B5/04525 , A61B5/0456 , A61B5/0468 , A61B5/7246 , A61B5/7275 , A61N1/36053 , A61N1/36064
摘要： Methods, systems, and apparatus for detecting and/or validating a detection of a state change by matching the shape of one or more of an cardiac data series, a heart rate variability data series, or at least a portion of a heart beat complex, derived from cardiac data, to an appropriate template.

40. 发明授权

US09368395B1 Self-aligned via and air gap 有权
标题翻译：自对准通孔和气隙
公开(公告)号：US09368395B1
公开(公告)日：2016-06-14
申请号：US14270660
申请日：2014-05-06
申请人： GLOBALFOUNDRIES Inc.
发明人： Andy Chih-Hung Wei , Mark A. Zaleski
IPC分类号： H01L21/768 , H01L23/48
CPC分类号： H01L23/5226 , H01L21/76802 , H01L21/76805 , H01L21/76807 , H01L21/7682 , H01L21/76834 , H01L21/76877 , H01L21/76883 , H01L21/76897 , H01L23/481 , H01L23/5283 , H01L23/5329 , H01L29/0649
摘要： Provided are approaches for forming a self-aligned via and an air gap within a semiconductor device. Specifically, one approach produces a device having: a first metal line beneath a second metal line within an ultra low-k (ULK) dielectric, the first metal line connected to the second metal line by a first via; a dielectric capping layer formed over the second metal line; a third metal line within first and second via openings formed within a ULK fill material formed over the dielectric capping layer, wherein the third metal line within the first via opening extends to a top surface of the dielectric capping layer, and wherein the third metal line within the second via opening is connected to the second metal by a second via passing through the dielectric capping layer; and an air gap formed between the third metal line within the first and seconds via openings.
摘要翻译：提供了用于在半导体器件内形成自对准通孔和气隙的方法。具体地，一种方法产生一种器件，其具有：在超低k（ULK）电介质中的第二金属线下方的第一金属线，所述第一金属线通过第一通孔连接到所述第二金属线; 形成在所述第二金属线上的电介质覆盖层; 形成在形成在电介质覆盖层上的ULK填充材料内的第一和第二通孔内的第三金属线，其中第一通孔开口内的第三金属线延伸到介电覆盖层的顶表面，并且其中第三金属线在第二通孔开口内通过穿过电介质盖层的第二通孔连接到第二金属; 以及形成在第一和第二通孔之间的第三金属线之间的气隙。

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