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31. 发明授权

US07406080B2 Method and structure for enqueuing data packets for processing 失效
标题翻译：排队处理数据包的方法和结构
公开(公告)号：US07406080B2
公开(公告)日：2008-07-29
申请号：US10868725
申请日：2004-06-15
申请人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
发明人： Claude Basso , Jean L. Calvignac , Chih-jen Chang , Gordon T. Davis , Fabrice J. Verplanken
IPC分类号： H04L12/56
CPC分类号： H04L49/90 , H04L49/9042 , H04L49/9073 , H04L69/22
摘要： A method and structure is provided for buffering data packets having a header and a remainder in a network processor system. The network processor system has a processor on a chip and at least one buffer on the chip. Each buffer on the chip is configured to buffer the header of the packets in a preselected order before execution in the processor, and the remainder of the packet is stored in an external buffer apart from the chip. The method comprises utilizing the header information to identify the location and extent of the remainder of the packet. The entire selected packet is stored in the external buffer when the buffer of the stored header of the given packet is full, and moving only the header of a selected packet stored in the external buffer to the buffer on the chip when the buffer on the chip has space therefor.
摘要翻译：提供了一种在网络处理器系统中缓冲具有报头和余数的数据分组的方法和结构。网络处理器系统在芯片上具有处理器和芯片上的至少一个缓冲器。芯片上的每个缓冲器被配置为在处理器中执行之前以预先选择的顺序缓冲数据包的报头，并且数据包的剩余部分存储在与芯片分离的外部缓冲器中。该方法包括利用报头信息来识别分组的其余部分的位置和范围。当给定分组的存储报头的缓冲器已满时，整个所选分组被存储在外部缓冲器中，并且当芯片上的缓冲器仅将存储在外部缓冲器中的选定分组的报头移动到芯片上的缓冲器时有空间。

32. 发明授权

US07395517B2 Data aligner in reconfigurable computing environment 失效
标题翻译：可重构计算环境中的数据对齐器
公开(公告)号：US07395517B2
公开(公告)日：2008-07-01
申请号：US11230956
申请日：2005-09-20
申请人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
发明人： Fabrice Jean Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Louis Calvignac
IPC分类号： G06F17/50
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译：公开了可重构计算环境中的数据对准器。实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

33. 发明申请

US20080123662A1 Database Management System and Method of Using It to Transmit Packets 有权
标题翻译：数据库管理系统及其发送报文的方法
公开(公告)号：US20080123662A1
公开(公告)日：2008-05-29
申请号：US12015061
申请日：2008-01-16
申请人： Claude Basso , Natarajan Vaidhyanathan , Colin Beaton Verrilli
发明人： Claude Basso , Natarajan Vaidhyanathan , Colin Beaton Verrilli
IPC分类号： H04L12/56
CPC分类号： H04L45/54 , H04L12/56
摘要： A forwarding table, in a network device such as a router, used to forward packets in a communications network includes indicia whose state determine whether information contained in the forwarding table or information contained in the header portion of a packet is to be used to forward the packet to the next hop (i.e. next point in the route).
摘要翻译：用于在通信网络中转发分组的诸如路由器的网络设备中的转发表包括其状态确定包含在转发表中的信息或包含在分组的报头部分中的信息将被用于转发分组到下一跳（即路由中的下一个点）。

34. 发明授权

US07376809B2 Systems and methods for multi-frame control blocks 有权
标题翻译：多帧控制块的系统和方法
公开(公告)号：US07376809B2
公开(公告)日：2008-05-20
申请号：US11076218
申请日：2005-03-09
申请人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Chih-jen Chang , Fabrice Jean Verplanken
IPC分类号： G06F12/02
CPC分类号： H04L49/901 , H04L49/252 , H04L49/30 , H04L49/90 , H04L69/12 , H04L69/22
摘要： Systems and methods for implementing multi-frame control blocks in a network processor are disclosed. Embodiments include systems and methods to reduce long latency memory access to less expensive memory such as DRAM. As a network processor in a network receives packets of data, the network processor forms a frame control block for each packet. The frame control block contains a pointer to a memory location where the packet data is stored, and is thereby associated with the packet. The network processor associates a plurality of frame control blocks together in a table control block that is stored in a control store. Each table control block comprises a pointer to a memory location of a next table control block in a chain of table control blocks. Because frame control blocks are stored and accessed in table control blocks, less frequent memory accesses may be needed to keep up with the frame rate of packet transmission.
摘要翻译：公开了一种用于在网络处理器中实现多帧控制块的系统和方法。实施例包括用于减少长时间存储器访问到诸如DRAM之类的便宜的存储器的系统和方法。随着网络中的网络处理器接收数据包，网络处理器为每个数据包形成帧控制块。帧控制块包含指向存储分组数据的存储器位置的指针，并且因此与分组相关联。网络处理器将存储在控制存储器中的表控制块中的多个帧控制块相关联。每个表控制块包括指向表控制块链中的下一个表控制块的存储器位置的指针。由于帧控制块在表控制块中被存储和访问，因此可能需要较少频率的存储器访问以跟上分组传输的帧速率。

35. 发明授权

US07362744B2 Database management system and method of using it to transmit packets 有权
标题翻译：数据库管理系统及其使用方法传输数据包
公开(公告)号：US07362744B2
公开(公告)日：2008-04-22
申请号：US10219643
申请日：2002-08-15
申请人： Claude Basso , Natarajan Vaidhyanathan , Colin Beaton Verrilli
发明人： Claude Basso , Natarajan Vaidhyanathan , Colin Beaton Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L45/54 , H04L12/56
摘要： A forwarding table, in a network device such as a router, used to forward packets in a communications network includes indicia whose state determine whether information contained in the forwarding table or information contained in the header portion of a packet is to be used to forward the packet to the next hop (i.e. next point in the route).
摘要翻译：用于在通信网络中转发分组的诸如路由器的网络设备中的转发表包括其状态确定包含在转发表中的信息或包含在分组的报头部分中的信息将被用于转发分组到下一跳（即路由中的下一个点）。

36. 发明申请

US20070291782A1 ACKNOWLEDGEMENT FILTERING 审中-公开
标题翻译：确认过滤
公开(公告)号：US20070291782A1
公开(公告)日：2007-12-20
申请号：US11424043
申请日：2006-06-14
申请人： Claude Basso , Donald W. Schmidt , Venkat Venkatsubra
发明人： Claude Basso , Donald W. Schmidt , Venkat Venkatsubra
IPC分类号： H04L12/56 , H04L12/54 , H04L1/18
CPC分类号： H04L69/16 , H04L1/1838 , H04L1/1858 , H04L69/161 , H04L69/163 , H04L69/166 , H04L2001/0092
摘要： A solution for managing a communications connection, in which one or more acknowledgements are filtered is provided. In particular, data can be obtained for forwarding to a remote device, and at least some of the data can be communicated for processing on the remote device. Subsequently, an acknowledgement is received for the at least some of the data, and a determination is made as to whether to forward the acknowledgement based on an optimization configuration. The invention can include several checks to ensure that any acknowledgement that should be forwarded for further processing is properly forwarded. In one embodiment, the invention is implemented on a network adapter, and enables numerous acknowledgements that are received by the network adapter for a large send data packet to be filtered and not provided to a protocol stack.
摘要翻译：提供用于管理通信连接的解决方案，其中一个或多个确认被过滤。特别地，可以获得用于转发到远程设备的数据，并且可以传送至少一些数据以在远程设备上进行处理。随后，接收至少一些数据的确认，并且基于优化配置确定是否转发确认。本发明可以包括若干检查，以确保应转发用于进一步处理的任何确认被正确转发。在一个实施例中，本发明在网络适配器上实现，并且允许由网络适配器接收的大量发送数据分组的许多确认被过滤并且不提供给协议栈。

37. 发明授权

US07310685B2 Method and system for reducing look-up time in packet forwarding on computer networks 失效
标题翻译：减少计算机网络上数据包转发查找时间的方法和系统
公开(公告)号：US07310685B2
公开(公告)日：2007-12-18
申请号：US10230921
申请日：2002-08-29
申请人： Claude Basso , Bay Van Nguyen , Max Robert Povse , Natarajan Vaidhyanathan , Colin Beaton Verrilli
发明人： Claude Basso , Bay Van Nguyen , Max Robert Povse , Natarajan Vaidhyanathan , Colin Beaton Verrilli
IPC分类号： H04L12/28
CPC分类号： H04L29/00 , H04L45/742
摘要： A method and system for reducing the lookup time in packet forwarding on computer networks. A first lookup is performed in a memory tree to find a first protocol forwarding entry in the memory tree. The forwarding entry includes first protocol (e.g., EGP) information and cached associated second protocol (e.g., IGP) information. Both EGP and IGP information are retrievable with the first lookup and used in the determination of an EGP route for the data packet. If the cached IGP information has been invalidated due to address updates, a second lookup can be performed to find an original IGP entry in the memory tree, the information from which can be cached in the EGP forwarding entry if a background maintenance task has finished designating all the EGP entries as having out-of-date caches.
摘要翻译：一种用于减少计算机网络上的分组转发中的查找时间的方法和系统。在存储器树中执行第一次查找以在存储器树中找到第一协议转发条目。转发条目包括第一协议（例如，EGP）信息和缓存的相关联的第二协议（例如，IGP）信息。 EGP和IGP信息都可以通过第一次查找进行检索，并用于确定数据包的EGP路由。如果缓存的IGP信息由于地址更新而被无效，则可以执行第二次查找以在存储器树中找到原始IGP条目，如果后台维护任务已经完成指定，则可以将其从EGP转发条目缓存到其中所有EGP条目都具有过期缓存。

38. 发明申请

US20070223389A1 Methods and apparatus for improving security while transmitting a data packet 失效
标题翻译：用于在传输数据分组时提高安全性的方法和装置
公开(公告)号：US20070223389A1
公开(公告)日：2007-09-27
申请号：US11388011
申请日：2006-03-23
申请人： Claude Basso , Jean Calvignac , Ronald Fuhs , Nathaniel Sellin , Colin Verrilli , Scott Willenborg
发明人： Claude Basso , Jean Calvignac , Ronald Fuhs , Nathaniel Sellin , Colin Verrilli , Scott Willenborg
IPC分类号： H04J1/16 , H04L12/66
CPC分类号： H04L49/9042 , H04L49/90 , H04L69/22
摘要： In a first aspect, a first method of transmitting a data packet is provided. The first method includes the steps of (1) for each connection from which a data packet may be transmitted, storing header data corresponding to the connection; (2) employing a user application to form header and payload data of a packet, wherein the user application is associated with a connection from which the packet is to be transmitted; and (3) while transmitting the packet, comparing one or more portions of the packet header data with the header data corresponding to the connection with which the user application is associated. Numerous other aspects are provided.
摘要翻译：在第一方面，提供了发送数据分组的第一种方法。第一种方法包括以下步骤：（1）对于可以从其发送数据分组的每个连接，存储对应于该连接的头部数据; （2）使用用户应用来形成分组的报头和有效载荷数据，其中所述用户应用与要发送所述分组的连接相关联; 和（3）在发送分组时，将分组报头数据的一个或多个部分与对应于用户应用所关联的连接的报头数据进行比较。提供了许多其他方面。

39. 发明授权

US07200696B2 System method structure in network processor that indicates last data buffer of frame packet by last flag bit that is either in first or second position 失效
标题翻译：网络处理器中的系统方法结构，通过最后一个标志位指示帧分组的最后数据缓冲区，处于第一或第二位置
公开(公告)号：US07200696B2
公开(公告)日：2007-04-03
申请号：US09828342
申请日：2001-04-06
申请人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
发明人： Claude Basso , Jean Louis Calvignac , Marco C. Heddes , Joseph Franklin Logan , Fabrice Jean Verplanken
IPC分类号： G06F15/16
CPC分类号： H04L49/901 , H04L49/103 , H04L49/3018 , H04L49/90 , H04L49/9094
摘要： A method and structure for determining when a frame of information comprised of one or more buffers of data being transmitted in a network processor has completed transmission is provided. The network processor includes a plurality of control blocks, one for each data buffer, each containing control information to link one buffer to another for transmission. Each of the control blocks has a last bit feature which is a single bit and indicates when the data buffer having the last bit is transmitted. This last bit feature is a bit which can be set to either zero or one. The last bit feature is in a first position when an additional data buffer is to be chained to a previous data buffer indicating an additional data buffer is to be transmitted and a second position when no additional data buffer is to be chained to a previous data buffer. The position of the last bit feature is communicated to the network processor to indicate whether the transmission of a particular frame is ended and a new frame is to be transmitted.
摘要翻译：提供了一种用于确定在网络处理器中正在发送的一个或多个数据缓冲器组成的信息帧何时完成传输的方法和结构。网络处理器包括多个控制块，一个用于每个数据缓冲器，每个控制块包含用于将一个缓冲器链接到另一缓冲器以进行传输的控制信息。每个控制块具有作为单个位的最后位特征，并且指示何时发送具有最后位的数据缓冲器。这最后一位功能是一个可以设置为零或一个的位。当附加数据缓冲器被链接到先前的数据缓冲器指示要发送附加数据缓冲器时，最后一位特征处于第一位置，而当没有附加数据缓冲器被链接到先前的数据缓冲器时，第二位置。将最后一位特征的位置传送给网络处理器，以指示特定帧的传输是否结束，并且要发送新的帧。

40. 发明申请

US20070067478A1 Data aligner in reconfigurable computing environment technical field 失效
标题翻译：数据对准器在可重构计算环境技术领域
公开(公告)号：US20070067478A1
公开(公告)日：2007-03-22
申请号：US11230956
申请日：2005-09-20
申请人： Fabrice Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Calvignac
发明人： Fabrice Verplanken , Jean-Paul Aldebert , Claude Basso , Jean Calvignac
IPC分类号： G06F15/16
CPC分类号： H04L69/16 , H04L49/45 , H04L69/161
摘要： A data aligner in a reconfigurable computing environment is disclosed. Embodiments employ hardware macros in field configurable gate arrays (FPGAs) to minimize the number of configurable logic blocks (CLBs) needed to shift bytes of data. The alignment mechanism allows flexibility, scalability, configurability, and reduced costs as compared to application specific integrated circuits.
摘要翻译：公开了可重构计算环境中的数据对准器。实施例使用现场可配置门阵列（FPGA）中的硬件宏来最小化移动数据字节所需的可配置逻辑块（CLB）的数量。与专用集成电路相比，对准机制允许灵活性，可扩展性，可配置性和降低的成本。

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