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1. 发明申请

US20180159803A1 HEADER REPLICATION IN ACCELERATED TCP (TRANSPORT CONTROL PROTOCOL) STACK PROCESSING 审中-公开
公开(公告)号：US20180159803A1
公开(公告)日：2018-06-07
申请号：US15832195
申请日：2017-12-05
申请人： Intel Corporation
发明人： Linden Cornett , David B. Minturn , Sujoy Sen , Hemal V. Shah , Anshuman Thakur , Gary Y. Tsao , Anil Vasudevan
IPC分类号： H04L12/861 , H04L29/06 , H04L12/863
CPC分类号： H04L49/9042 , H04L47/50 , H04L49/90 , H04L69/16 , H04L69/161 , H04L69/163
摘要： In one embodiment, a method is provided. The method of this embodiment provides storing a packet header at a set of at least one page of memory allocated to storing packet headers, and storing the packet header and a packet payload at a location not in the set of at least one page of memory allocated to storing packet headers.

2. 发明申请

US20180159802A1 DATA ENQUEUING METHOD, DATA DEQUEUING METHOD, AND QUEUE MANAGEMENT CIRCUIT 审中-公开
公开(公告)号：US20180159802A1
公开(公告)日：2018-06-07
申请号：US15883465
申请日：2018-01-30
申请人： HUAWEI TECHNOLOGIES CO., LTD.
发明人： Yalin BAO
IPC分类号： H04L12/861 , H04L12/721 , H04L12/883 , H04L12/773 , H04L12/879 , H04L12/873
CPC分类号： H04L49/9036 , H04L45/566 , H04L45/60 , H04L47/52 , H04L47/6275 , H04L49/109 , H04L49/901 , H04L49/9015 , H04L49/9021 , H04L49/9042
摘要： The disclosure describes a data enqueuing method. The method may include: receiving a to-be-enqueued data packet, dividing the data packet into several slices to obtain slice information of the slices, and marking a tail slice of the data packet with a tail slice identifier; enqueuing corresponding slice information according to an order of the slices in the data packet, and in a process of enqueuing the corresponding slice information, if a slice is marked with the tail slice identifier, determining that the slice is the tail slice of the data packet, and generating a first-type node; and determining whether a target queue is empty, and if the target queue is empty, writing slice information of the tail slice into the target queue, and updating a head pointer of a queue head list according to the first-type node.

3. 发明授权

US09985896B2 Caching of service decisions 有权
公开(公告)号：US09985896B2
公开(公告)日：2018-05-29
申请号：US14574335
申请日：2014-12-17
申请人： Nicira, Inc.
发明人： Teemu Koponen , Ethan J. Jackson
IPC分类号： H04L12/851 , G06F12/0811 , G06F12/128 , H04L12/911 , H04L12/861 , H04L12/715 , H04L12/751 , H04L12/741 , H04L12/721
CPC分类号： H04L47/2441 , G06F12/0811 , G06F12/128 , G06F2212/283 , G06F2212/69 , G06F2212/70 , H04L45/02 , H04L45/38 , H04L45/64 , H04L45/745 , H04L47/827 , H04L49/9042
摘要： Some embodiments provide a method for processing a packet received by a managed forwarding element. The method performs a series of packet classification operations based on header values of the received packet. The packet classifications operations determine a next destination of the received packet. When the series of packet classification operations specifies to send the packet to a network service that performs payload transformations on the packet, the method (1) assigns a service operation identifier to the packet that identifies the service operations for the network service to perform on the packet, (2) sends the packet to the network service with the service operation identifier, and (3) stores a cache entry for processing subsequent packets without the series of packet classification operations. The cache entry includes the assigned service operation identifier. The network service uses the assigned service operation identifier to process packets without performing its own classification operations.

4. 发明申请

US20170353403A1 PACKET DESCRIPTOR STORAGE IN PACKET MEMORY WITH CACHE 审中-公开
公开(公告)号：US20170353403A1
公开(公告)日：2017-12-07
申请号：US15610909
申请日：2017-06-01
申请人： Marvell Israel (M.I.S.L) Ltd.
发明人： Rami ZEMACH , Dror BROMBERG
IPC分类号： H04L12/883 , G06F3/06 , G06F5/14 , H04L12/861 , H04L12/863
CPC分类号： H04L49/9015 , G06F3/0659 , H04L47/6245 , H04L49/103 , H04L49/9005 , H04L49/9026 , H04L49/9042 , H04L49/9078
摘要： A first memory device stores (i) a head part of a FIFO queue structured as a linked list (LL) of LL elements arranged in an order in which the LL elements were added to the FIFO queue and (ii) a tail part of the FIFO queue. A second memory device stores a middle part of the FIFO queue, the middle part comprising a LL elements following, in an order, the head part and preceding, in the order, the tail part. A queue controller retrieves LL elements in the head part from the first memory device, moves LL elements in the middle part from the second memory device to the head part in the first memory device prior to the head part becoming empty, and updates LL parameters corresponding to the moved LL elements to indicate storage of the moved LL elements changing from the second memory device to the first memory device.

5. 发明申请

US20170331881A1 Digital Signal Processing Over Data Streams 审中-公开
公开(公告)号：US20170331881A1
公开(公告)日：2017-11-16
申请号：US15152369
申请日：2016-05-11
申请人： Microsoft Technology Licensing, LLC
发明人： Badrish Chandramouli , Jonathan D. Goldstein , Milos Nikolic
IPC分类号： H04L29/08 , H04L12/911 , H04L12/861
CPC分类号： H04L67/10 , G06F17/30442 , H04L47/82 , H04L49/9042 , H04L67/12
摘要： The techniques and systems described herein are directed to providing deep integration of digital signal processing (DSP) operations with a general-purpose query processor. The techniques and systems provide a unified query language for processing tempo-relational and signal data, provide mechanisms for defining DSP operators, and support incremental computation in both offline and online analysis. The techniques and systems include receiving streaming data, aggregating and performing uniformity processing to generate a uniform signal, and storing the uniform signal in a batched columnar representation. Data can be copied from the batched columnar representation to a circular buffer, where DSP operations are applied to the data. Incremental processing can avoid redundant processing. Improvements to the functioning of a computer are provided by reducing an amount of data that to be passed back and forth between separate query databases and DSP processors, and by reducing a latency of processing and/or memory usage.

6. 发明授权

US09787613B2 Decoupled packet and data processing rates in switch devices 有权
公开(公告)号：US09787613B2
公开(公告)日：2017-10-10
申请号：US14755485
申请日：2015-06-30
申请人： AVAGO TECHNOLOGIES GENERAL IP (SINGAPORE) PTE. LTD.
发明人： Mark David Griswold , Michael Hei-Lung Lau
IPC分类号： H04L12/28 , H04L12/861 , H04L12/935 , H04L12/873
CPC分类号： H04L49/9057 , H04L47/52 , H04L49/3072 , H04L49/9042
摘要： Continuing to integrate more aggregate bandwidth and higher radix into switch devices is an economic imperative because it creates value both for the supplier and customer in large data center environments which are an increasingly important part of the marketplace. While new silicon processes continue to shrink transistor and other chip feature dimensions, process technology cannot be relied upon as a key driver of power reduction. Transitioning from 28 nm to 16 nm is a special case where FinFET provides additional power scaling, but subsequent FinFET nodes are not expected to deliver as substantial of power reductions to meet the desired increases in integration. The disclosed switch architecture attacks the power consumption problem by controlling the rate at which power-consuming activities occur.

7. 发明授权

US09712442B2 Efficient memory bandwidth utilization in a network device 有权
公开(公告)号：US09712442B2
公开(公告)日：2017-07-18
申请号：US14072744
申请日：2013-11-05
申请人： BROADCOM CORPORATION
发明人： David Wu , Darren Duane Neuman , Flaviu Dorin Turean , Rajesh Shankarrao Mamidwar , Anand Tongle , Predrag Kostic
IPC分类号： H04L12/879 , H04L12/861 , H04L12/747
CPC分类号： H04L45/742 , H04L49/901 , H04L49/9042 , H04L49/9047 , H04L49/9078
摘要： A system for efficient memory bandwidth utilization may include a depacketizer, a packetizer, and a processor core. The depacketizer may generate header information items from received packets, where the header information items include sufficient information for the processor core to process the packets without accessing the payloads from off-chip memory. The depacketizer may accumulate multiple payloads and may write the multiple payloads to the off-chip memory in a single memory transaction when a threshold amount of the payloads have been accumulated. The processor core may receive the header information items and may generate a single descriptor for accessing multiple payloads corresponding to the header information items from the off-chip memory. The packetizer may generate a header for each payload based at least on on-chip information and without accessing off-chip memory. Thus, the subject system provides efficient memory bandwidth utilization, e.g. at least by reducing the number of off-chip memory accesses.

8. 发明授权

US09608940B2 Ultra low latency network buffer storage 有权
公开(公告)号：US09608940B2
公开(公告)日：2017-03-28
申请号：US14658711
申请日：2015-03-16
申请人： Cisco Technology, Inc.
发明人： Kelvin Chan , Ganga S. Devadas , Chih-Tsung Huang , Wei-Jen Huang , Dennis K. D. Nguyen , Yue J. Yang
IPC分类号： G06F15/173 , H04L12/861 , G06F15/167
CPC分类号： H04L49/9042 , G06F15/167 , H04L49/9057 , H04L49/9094
摘要： Buffer designs and write/read configurations for a buffer in a network device are provided. According to one aspect, a first portion of the packet is written into a first cell of a plurality of cells of a buffer in the network device. Each of the cells has a size that is less than a minimum size of packets received by the network device. The first portion of the packet can be read from the first cell while concurrently writing a second portion of the packet to a second cell.

9. 发明申请

US20160085477A1 ADDRESSLESS MERGE COMMAND WITH DATA ITEM IDENTIFIER 审中-公开
标题翻译：无数据统一命令与数据项标识符
公开(公告)号：US20160085477A1
公开(公告)日：2016-03-24
申请号：US14492013
申请日：2014-09-20
申请人： Netronome Systems, Inc.
发明人： Salma Mirza , Gavin J. Stark
IPC分类号： G06F3/06 , G06F13/28 , G06F12/02
CPC分类号： G06F3/0647 , G06F3/0611 , G06F3/0656 , G06F3/0683 , G06F13/28 , H04L12/00 , H04L12/6418 , H04L29/08 , H04L47/35 , H04L47/624 , H04L49/3072 , H04L49/9042 , H04L69/22
摘要： An addressless merge command includes an identifier of an item of data, and a reference value, but no address. A first part of the item is stored in a first place. A second part is stored in a second place. To move the first part so that the first and second parts are merged, the command is sent across a bus to a device. The device translates the identifier into a first address ADR1, and uses ADR1 to read the first part. Stored in or with the first part is a second address ADR2 indicating where the second part is stored. The device extracts ADR2, and uses ADR1 and ADR2 to issue bus commands. Each bus command causes a piece of the first part to be moved. When the entire first part has been moved, then device returns the reference value to indicate that the merge command has been completed.
摘要翻译：无地址合并命令包括数据项的标识符和参考值，但没有地址。项目的第一部分存储在第一个位置。第二部分存储在第二部分。要移动第一部分以使第一部分和第二部分合并，命令通过总线发送到设备。设备将标识符转换为第一地址ADR1，并使用ADR1读取第一部分。存储在第一部分中或与第一部分一起存储是指示第二部分被存储在哪里的第二地址ADR2。该设备提取ADR2，并使用ADR1和ADR2发出总线命令。每个总线命令使第一部分的一部分被移动。当整个第一部分被移动时，设备返回参考值以指示合并命令已经完成。

10. 发明授权

US09025608B2 Route switching device and data cashing method thereof 有权
标题翻译：路由切换设备及其数据融合方法
公开(公告)号：US09025608B2
公开(公告)日：2015-05-05
申请号：US13393632
申请日：2010-05-24
申请人： Hongqi Chen , Chang Zhou
发明人： Hongqi Chen , Chang Zhou
IPC分类号： G06F13/28 , H04L29/08 , H04L12/861
CPC分类号： H04L67/2842 , H04L49/9042 , H04L49/9078
摘要： The present invention discloses a routing and switching device and a data caching method thereof. The method includes: a routing and switching device, when receiving a data packet, and if the routing and switching device inquires that a data caching state of an exterior cache is that there are data slice row addresses not fully filled and continuous space in the data slice row addresses not fully filled is enough to store all the data slices of the data packet, then writing all the data slices of the data packet into the data slice row addresses not fully filled, storing packet information of the data packet and the written data slice row addresses, and updating the data caching state of the exterior cache. The present invention enhances the utilization rate of the memory bandwidth. In addition, the present invention is also easy to be applied in other relevant data caching managements.
摘要翻译：本发明公开了一种路由切换装置及其数据缓存方法。该方法包括：路由和交换设备，当接收到数据包时，如果路由和交换设备询问外部高速缓存的数据高速缓存状态是否存在未完全填充的数据切片行地址和数据中的连续空间片段行地址未完全填充就足以存储数据包的所有数据片段，然后将数据包的所有数据片段写入未完全填充的数据片段行地址，存储数据包的包信息和写入数据切片行地址，并更新外部缓存的数据高速缓存状态。本发明提高了存储器带宽的利用率。此外，本发明也容易应用于其他相关的数据缓存管理。

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