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31. 发明申请

US20170098081A1 EVENT-BASED APPARATUS AND METHOD FOR SECURING BIOS IN A TRUSTED COMPUTING SYSTEM DURING EXECUTION 审中-公开
公开(公告)号：US20170098081A1
公开(公告)日：2017-04-06
申请号：US15380762
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. Glenn HENRY
IPC分类号： G06F21/57 , G06F13/42 , H04L9/32 , G06F9/44 , H04L29/06
CPC分类号： G06F21/572 , G06F9/4401 , G06F13/4282 , G06F21/554 , G06F2221/2107 , H04L9/3242
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of an APIC access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

32. 发明申请

US20170098079A1 EVENT-BASED APPARATUS AND METHOD FOR SECURING BIOS IN A TRUSTED COMPUTING SYSTEM DURING EXECUTION 有权
公开(公告)号：US20170098079A1
公开(公告)日：2017-04-06
申请号：US15380661
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. GLENN HENRY
IPC分类号： G06F21/57 , G06F13/42 , H04L9/32 , G06F9/44 , H04L29/06
CPC分类号： G06F21/572 , G06F9/4401 , G06F13/24 , G06F13/4282 , G06F21/554 , G06F2221/2107 , H04L9/06 , H04L9/0618 , H04L9/0869 , H04L9/3231 , H04L9/3242 , H04L63/0435 , H04L63/0876 , H04L63/123
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of an operating system call. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

33. 发明申请

US20170098078A1 EVENT-BASED APPARATUS AND METHOD FOR SECURING BIOS IN A TRUSTED COMPUTING SYSTEM DURING EXECUTION 有权
公开(公告)号：US20170098078A1
公开(公告)日：2017-04-06
申请号：US15380063
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. GLENN HENRY
IPC分类号： G06F21/57 , H04L9/32 , G06F13/24 , G06F13/42 , G06F9/44 , H04L29/06
CPC分类号： G06F21/572 , G06F9/4401 , G06F13/24 , G06F13/4282 , G06F21/554 , G06F2221/2107 , H04L9/06 , H04L9/0618 , H04L9/0869 , H04L9/3231 , H04L9/3242 , H04L63/0435 , H04L63/0876 , H04L63/123
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a PCI Express access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

34. 发明申请

US20170098077A1 EVENT-BASED APPARATUS AND METHOD FOR SECURING BIOS IN A TRUSTED COMPUTING SYSTEM DURING EXECUTION 有权
公开(公告)号：US20170098077A1
公开(公告)日：2017-04-06
申请号：US15380015
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. GLENN HENRY
IPC分类号： G06F21/57 , H04L9/32 , G06F13/24 , G06F13/42 , G06F9/44 , H04L29/06
CPC分类号： G06F21/572 , G06F9/4401 , G06F13/24 , G06F13/4282 , G06F21/554 , G06F2221/2107 , H04L9/06 , H04L9/0618 , H04L9/0869 , H04L9/3231 , H04L9/3242 , H04L63/0435 , H04L63/0876 , H04L63/123
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a change in virtual memory mapping. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

35. 发明申请

US20170098076A1 EVENT-BASED APPARATUS AND METHOD FOR SECURING BIOS IN A TRUSTED COMPUTING SYSTEM DURING EXECUTION 有权
公开(公告)号：US20170098076A1
公开(公告)日：2017-04-06
申请号：US15379974
申请日：2016-12-15
申请人： VIA TECHNOLOGIES, INC.
发明人： G. GLENN HENRY
IPC分类号： G06F21/57 , H04L9/32 , G06F13/24 , G06F13/42 , G06F9/44 , H04L29/06
CPC分类号： G06F21/572 , G06F9/4401 , G06F13/24 , G06F13/4282 , G06F21/554 , G06F2221/2107 , H04L9/06 , H04L9/0618 , H04L9/0869 , H04L9/3231 , H04L9/3242 , H04L63/0435 , H04L63/0876 , H04L63/123
摘要： An apparatus is provided for protecting a basic input/output system (BIOS) in a computing system. The apparatus includes a BIOS read only memory (ROM), an event detector, and a tamper detector. The BIOS ROM has BIOS contents that are stored as plaintext, and an encrypted message digest, where the encrypted message digest comprises an encrypted version of a first message digest that corresponds to the BIOS contents, and where and the encrypted version is generated via a symmetric key algorithm and a key. The event detector is configured to generate a BIOS check interrupt that interrupts normal operation of the computing system upon the occurrence of an event, where the event includes one or more occurrences of a hard disk access. The tamper detector is operatively coupled to the BIOS ROM and is configured to access the BIOS contents and the encrypted message digest upon assertion of the BIOS check interrupt, and is configured to direct a microprocessor to generate a second message digest corresponding to the BIOS contents and a decrypted message digest corresponding to the encrypted message digest using the symmetric key algorithm and the key, and is configured to compare the second message digest with the decrypted message digest, and configured to preclude the operation of the microprocessor if the second message digest and the decrypted message digest are not equal. The microprocessor includes a dedicated crypto/hash unit disposed within execution logic, where the crypto/hash unit generates the second message digest and the decrypted message digest, and where the key is exclusively accessed by the crypto/hash unit. The microprocessor further has a random number generator disposed within the execution logic, where the random number generator generates a random number at completion of a current BIOS check, which is employed by the event detector to randomly set a number of occurrences of the event that are to occur before a following BIOS check.

36. 发明授权

US09606951B2 External electronic device and interface controller and external electronic device control method 有权
公开(公告)号：US09606951B2
公开(公告)日：2017-03-28
申请号：US14152343
申请日：2014-01-10
申请人： VIA TECHNOLOGIES, INC.
发明人： Chia-Ying Kuo
IPC分类号： G06F13/40 , G06F13/14 , G06F9/44
CPC分类号： G06F13/4027 , G06F9/4411 , G06F13/14 , G06F2213/0042
摘要： An interface controller, coupling a device main body of an external electronic device to a host, is disclosed, which transmits a termination-on signal to the host prior to a mechanically stable state of a device main body of the external electronic device. When the device main body has not reached the mechanically stable state yet, the interface controller responds to the host with default link information in a delayed manner. The default link information is contained in the interface controller. When the device main body reaches the mechanically stable state, the interface controller transmits specific link information retrieved from the device main body to the host.

37. 发明授权

US09606597B2 Intermediate electronic device, method for operating the intermediate electronic device and electronic system 有权
公开(公告)号：US09606597B2
公开(公告)日：2017-03-28
申请号：US14205790
申请日：2014-03-12
申请人： VIA TECHNOLOGIES, INC.
发明人： Yi-Te Chen
IPC分类号： G06F1/26 , H02J1/00 , H02J1/10
CPC分类号： G06F1/26 , G06F1/266 , H02J1/10
摘要： An intermediate electronic device, arranged to be coupled to a host system and an electronic device. The intermediate electronic device includes: a controller, enabled by an enable signal to process the data transmission between the host system and the electronic device; and a power transmission unit disposed between the host system and the electronic device. The power transmission units detect whether the power transmission unit is coupled to the host system or an external power source. When the power transmission unit detects that the power transmission unit is coupled to the host system, but not coupled to the external power source, the power transmission unit informs the host system to raise the voltage output to the intermediate electronic device to supply power to the electronic device, and outputs the enable signal.

38. 发明授权

US09588769B2 Processor that leapfrogs MOV instructions 有权
标题翻译：处理器跳过MOV指令
公开(公告)号：US09588769B2
公开(公告)日：2017-03-07
申请号：US14315122
申请日：2014-06-25
申请人： VIA TECHNOLOGIES, INC.
发明人： Gerard M. Col , Matthew Daniel Day
IPC分类号： G06F9/30 , G06F9/38
CPC分类号： G06F9/30069 , G06F9/30032 , G06F9/384 , G06F9/3855
摘要： A processor performs out-of-order execution of a first instruction and a second instruction after the first instruction in program order, the first instruction includes source and destination indicators, the source indicator specifies a source of data, the destination indicator specifies a destination of the data, the first instruction instructs the processor to move the data from the source to the destination, the second instruction specifies a source indicator that specifies a source of data. A rename unit updates the second instruction source indicator with the first instruction source indicator if there are no intervening instructions that write to the source or to the destination of the first instruction and the second instruction source indicator matches the first instruction destination indicator.
摘要翻译：处理器以程序顺序执行在第一指令之后的第一指令和第二指令的无序执行，第一指令包括源和目标指示符，源指示符指定数据源，目的地指示符指定数据，第一指令指示处理器将数据从源移动到目的地，第二指令指定指定数据源的源指示符。如果没有写入到第一指令的源或目的地的第二指令源指示符，并且第二指令源指示符与第一指令目标指示符匹配，则重命名单元用第一指令源指示符更新第二指令源指示符。

39. 发明授权

US09583555B2 Semiconductor device having inductor 有权
标题翻译：具有电感器的半导体器件
公开(公告)号：US09583555B2
公开(公告)日：2017-02-28
申请号：US14813510
申请日：2015-07-30
申请人： VIA TECHNOLOGIES, INC.
发明人： Sheng-Yuan Lee
IPC分类号： H01L23/522 , H01L49/02 , H01L27/02
CPC分类号： H01L28/10 , H01L23/5227 , H01L27/0248 , H01L2924/0002 , H01L2924/00
摘要： A semiconductor device including a first insulating layer and a second insulating layer sequentially disposed on a substrate having a center region. The semiconductor device includes a first winding portion and a second winding portion disposed in the second insulating layer and surrounding the center region A second conductive line and a third conductive line are arranged from the inside to the outside. In addition, each of the first, second and third conductive lines has a first end and a second end. The semiconductor device also includes a coupling portion disposed in the first and second insulating layers between the first and second winding portions, and having a first pair of connection layers cross-connecting the second ends of the first and second conductive lines, and a second pair of connection layers cross-connecting the first ends of the second and third conductive lines.
摘要翻译：一种半导体器件，包括顺序地设置在具有中心区域的衬底上的第一绝缘层和第二绝缘层。半导体器件包括设置在第二绝缘层中并围绕中心区域的第一绕组部分和第二绕组部分，从内向外布置第二导线和第三导线。此外，第一，第二和第三导线中的每一个具有第一端和第二端。该半导体器件还包括一个耦合部分，设置在第一和第二绕组部分之间的第一和第二绝缘层中，并具有交叉连接第一和第二导线的第二端的第一对连接层，以及第二对的连接层交叉连接第二和第三导线的第一端。

40. 发明授权

US09582670B2 Data storage device and data scrambling and descrambling method 有权
标题翻译：数据存储设备和数据加扰解扰法
公开(公告)号：US09582670B2
公开(公告)日：2017-02-28
申请号：US14463991
申请日：2014-08-20
申请人： VIA TECHNOLOGIES, INC.
发明人： Lei Feng
IPC分类号： G06F21/60 , G06F21/79 , G06F21/85
CPC分类号： G06F21/602 , G06F21/79 , G06F21/85
摘要： A data scrambling and descrambling technology based on logical addresses. A data storage device with the data scrambling and descrambling technology includes a non-volatile memory and a controller. The controller generates a data scrambling seed according to a logical writing address issued from the host, scrambles the write data issued from the host with the data scrambling seed and then stores the scrambled write data into the non-volatile memory. The controller further generates a data descrambling seed according to a logical reading address issued from the host, and descrambles the read data retrieved from the non-volatile memory by the data descrambling seed. The controller further processes the descrambled read data for data checking and correction.
摘要翻译：基于逻辑地址的数据加扰和解扰技术。具有数据加扰和解扰技术的数据存储设备包括非易失性存储器和控制器。控制器根据从主机发出的逻辑写入地址生成数据加扰种子，用数据加扰种子对从主机发出的写入数据进行加扰，然后将加扰的写入数据存储到非易失性存储器中。控制器还根据从主机发出的逻辑读取地址生成数据解扰种子，并通过数据解扰种子解扰从非易失性存储器检索的读取数据。控制器进一步处理解扰的读取数据用于数据检查和校正。

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