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31. 发明授权

US10795818B1 Method and apparatus for ensuring real-time snoop latency 有权
公开(公告)号：US10795818B1
公开(公告)日：2020-10-06
申请号：US16418811
申请日：2019-05-21
申请人： Apple Inc.
发明人： Harshavardhan Kaushikkar , Per H. Hammarlund , Brian P. Lilly , Michael Bekerman , James Vash , Manu Gulati , Benjamin K. Dodge
IPC分类号： G06F12/08 , G06F12/0815 , G06F12/0817
摘要： Various systems and methods for ensuring real-time snoop latency are disclosed. A system includes a processor and a cache controller. The cache controller receives, via a channel, cache snoop requests from the processor, the snoop requests including latency-sensitive and non-latency sensitive requests. Requests are not prioritized by type within the channel. The cache controller limits a number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop requests. Limiting the number of non-latency sensitive snoop requests that can be processed ahead of an incoming latency-sensitive snoop request includes the cache controller determining that the number of received non-latency sensitive snoop requests has reached a predetermined value and responsively prioritizing latency-sensitive requests over non-latency sensitive requests.

32. 发明授权

US10042701B2 Storing address of spare in failed memory location 有权
公开(公告)号：US10042701B2
公开(公告)日：2018-08-07
申请号：US15273208
申请日：2016-09-22
申请人： Apple Inc.
发明人： Manu Gulati , Sukalpa Biswas , Jeffrey R. Wilcox , Farid Nemati
IPC分类号： G06F11/10 , G11C29/52 , G11C29/00 , G06F12/1072 , G06F12/121 , G06F12/12 , G06F12/06 , G06F12/126 , G11C29/04 , G11C29/44
摘要： In one embodiment, a system includes a memory that includes a live section and a spares section. The live section may be mapped to the address space of the system, and may be accessed in response to memory operations. Once an entry in the live section has been detected as failed, an entry is in the spares section may be allocated to replace the failed entry. During subsequent accesses to the failed entry, the allocated entry may be used instead. In an embodiment, the failed entry may be coded with an indication of the allocated entry, to redirect to the allocated entry. In one implementation, for example, the failed entry may be coded with N copies of a pointer to the allocated entry, each copy protected by corresponding ECC.

33. 发明授权

US09928838B2 Clock switching in always-on component 有权
公开(公告)号：US09928838B2
公开(公告)日：2018-03-27
申请号：US15482142
申请日：2017-04-07
申请人： Apple Inc.
发明人： Manu Gulati , Gilbert H. Herbeck , Alexei E. Kosut , Girault W. Jones , Timothy J. Millet
IPC分类号： G10L15/28 , G10L19/00 , G10L15/22 , G10L15/08
CPC分类号： G10L15/28 , G10L15/08 , G10L15/22 , G10L2015/088 , G10L2015/223
摘要： In an embodiment, a system on a chip (SOC) may include one or more central processing units (CPUs), a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples and match those audio samples against a predetermined pattern. The circuit may operate according to a first clock during the time that the rest of the SOC is powered down. In response to detecting the predetermined pattern in the samples, the circuit may cause the memory controller and processors to power up. During the power up process, a second clock having one or more better characteristics than the first clock may become available. The circuit may switch to the second clock while preserving the samples, or losing at most one sample, or no more than a threshold number of samples.

34. 发明申请

US20180032281A1 SYSTEM FOR MANAGING MEMORY DEVICES 审中-公开
公开(公告)号：US20180032281A1
公开(公告)日：2018-02-01
申请号：US15225343
申请日：2016-08-01
申请人： Apple Inc.
发明人： Manu Gulati , Peter F. Holland , Erik P. Machnicki , Robert E. Jeter , Rakesh L. Notani , Neeraj Parik , Marc A. Schaub
IPC分类号： G06F3/06 , G11C11/406
CPC分类号： G06F3/0656 , G06F3/0604 , G06F3/0683 , G06F13/1673 , G11C11/40615
摘要： In some embodiments, a system includes a memory system, a real-time computing device, and a controller. The real-time computing device stores data within a local buffer having a corresponding storage threshold, where the data satisfies the storage threshold, and where the storage threshold is based on a latency of the memory system and an expected rate of utilization of the data of the local buffer. The controller detects that the memory system should perform an operation, where the memory system is unavailable to the real-time computing device during the operation. In response to detecting that an amount of time for the operation exceeds an amount of time corresponding to the storage threshold, the controller overrides the storage threshold. The controller may override the storage threshold by modifying the storage threshold and by overriding a default priority for access requests of the real-time computing device to the memory system.

35. 发明授权

US09811142B2 Low energy processor for controlling operating states of a computer system 有权
公开(公告)号：US09811142B2
公开(公告)日：2017-11-07
申请号：US14499807
申请日：2014-09-29
申请人： Apple Inc.
发明人： Cyril de la Cropte de Chanterac , Manu Gulati , Erik P. Machnicki , Keith Cox , Timothy J. Millet
IPC分类号： G06F1/32
CPC分类号： G06F1/3234 , G06F1/3203 , G06F1/3206 , G06F1/324 , G06F1/3243 , G06F1/3296 , Y02D10/126 , Y02D10/152 , Y02D10/172
摘要： Embodiments of a method that allow the adjustment of performance settings of a computing system are disclosed. One or more functional units may include multiple monitor circuits, each of which may be configured to monitor a given operational parameter of a corresponding functional unit. Upon detection of an event related to a monitored operational parameter, a monitor circuit may generate an interrupt. In response to the interrupt a processor may adjust one or more performance settings of the computing system.

36. 发明授权

US09698797B1 Hierarchical feedback-controlled oscillator techniques 有权
公开(公告)号：US09698797B1
公开(公告)日：2017-07-04
申请号：US15210852
申请日：2016-07-14
申请人： Apple Inc.
发明人： Manu Gulati , Suhas Kumar Suvarna Ramesh , Venkata Ramana Malladi , Thomas H. Huang , Rakesh L. Notani , Robert E. Jeter , Kai Lun Hsiung
IPC分类号： H03L7/00 , H03L7/07 , H03L7/099
CPC分类号： H03L7/23
摘要： Techniques are disclosed relating to feedback-controlled oscillators (e.g., phase-locked loops) arranged in two or more levels. In some embodiments, in a relatively higher-frequency mode, a first level feedback-controlled oscillator provides reference signals to one or more second level feedback-controlled oscillators that in turn generate output clock signals to clock sequential circuitry. In some embodiments, in a relatively lower-frequency mode, the first level feedback-controlled oscillator bypasses the second level feedback-controlled oscillators and provides output clock signals directly to sequential circuitry (without using any intervening feedback-controlled oscillators).

37. 发明申请

US20170177256A1 System on a Chip with Always-On Processor Which Reconfigures SOC and Supports Memory-Only Communication Mode 审中-公开
公开(公告)号：US20170177256A1
公开(公告)日：2017-06-22
申请号：US15447328
申请日：2017-03-02
申请人： Apple Inc.
发明人： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
IPC分类号： G06F3/06 , G06F9/44 , G06F13/16 , G06F13/42 , G11C11/406 , G06F13/40
CPC分类号： G06F12/0223 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F3/0625 , G06F3/0632 , G06F3/0634 , G06F3/0673 , G06F9/4406 , G06F12/0646 , G06F13/1668 , G06F13/4068 , G06F13/4265 , G06F2212/1032 , G11C11/40615 , Y02D10/122 , Y02D10/151 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

38. 发明申请

US20170168520A1 Timebase Synchronization 有权
公开(公告)号：US20170168520A1
公开(公告)日：2017-06-15
申请号：US14965073
申请日：2015-12-10
申请人： Apple Inc.
发明人： Shu-Yi Yu , Erik P. Machnicki , Gilbert H. Herbeck , Kiran B. Kattel , Manu Gulati
IPC分类号： G06F1/12
CPC分类号： G06F1/12 , G06F1/14
摘要： In an embodiment, an integrated circuit such as an SOC (or even a discrete chip system) includes one or more local timebases in various locations. The timebases may be incremented based on a high frequency local clock that may be subject to variation during use due. Periodically, based on a lower frequency clock that is subject to less variation, the local timebases may be synchronized to the correct time, using hardware circuitry. In particular, the correct timebase value for the next synchronization may be transmitted to each local timebase, and the control circuit for the local timebase may be configured to saturate the local timebase at the correct value if the local timebase reaches the correct value before the synchronization occurs. Similarly, if the synchronization occurs and the local timebase has not reached the correct value, the control circuit may be configured to load the correct timebase value.

39. 发明授权

US09659616B2 Configuration fuse data management in a partial power-on state 有权
公开(公告)号：US09659616B2
公开(公告)日：2017-05-23
申请号：US14459466
申请日：2014-08-14
申请人： Apple Inc.
发明人： Manu Gulati , Erik P. Machnicki , Gilbert H. Herbeck
IPC分类号： G11C17/16 , G11C7/20 , G11C29/04 , G11C29/44
CPC分类号： G11C7/20 , G11C17/16 , G11C2029/0407 , G11C2029/4402
摘要： In an embodiment, an apparatus may include a plurality of circuit blocks, a plurality of fuses and circuitry. The circuitry may be configured to determine a state for each of the plurality of fuses in response to transitioning from an off mode to a first operating mode. A first number of circuit blocks may be enabled in the first operating mode. The circuitry may also be configured to initialize the first number of circuit blocks dependent upon the states of one or more of the plurality of fuses and to transition from the first operating mode to a second operating mode. A second number of circuit blocks, less than the first number, may be enabled in the second operating mode. The circuitry may also be configured to store data representing the states of a subset of the plurality of fuses into a first memory enabled in the second operating mode.

40. 发明申请

US20160077579A1 METHOD FOR PREPARING A SYSTEM FOR A POWER LOSS 有权
标题翻译：制备电力损失系统的方法
公开(公告)号：US20160077579A1
公开(公告)日：2016-03-17
申请号：US14486491
申请日：2014-09-15
申请人： Apple Inc.
发明人： Manu Gulati , Tristan R. Hudson , Parin Patel , Fabien Faure
IPC分类号： G06F1/32 , G06F1/20
CPC分类号： G06F1/3296 , G06F1/206 , G06F1/30 , G06F1/3275 , Y02D10/14 , Y02D10/16 , Y02D10/172
摘要： In an embodiment, a system includes a power management unit (PMU), a non-volatile memory, a volatile memory, and a processor. The PMU may be configured to generate a power supply voltage, change a state of a status signal responsive to an event, and reduce a voltage level of the power supply voltage responsive to a predetermined period of time elapsing from detecting the event. The system may be configured to transition from a first to a second operating mode responsive to the change of the state of the status signal, and cancel pending commands to the non-volatile memory responsive to the transition to the second operating mode. The non-volatile memory may be configured to complete active commands prior the predetermined period of time elapsing.
摘要翻译：在一个实施例中，系统包括电源管理单元（PMU），非易失性存储器，易失性存储器和处理器。 PMU可以被配置为产生电源电压，响应于事件改变状态信号的状态，并且响应于从检测到事件经过的预定时间段来降低电源电压的电压电平。系统可以被配置为响应于状态信号的状态的改变而从第一操作模式转换到第二操作模式，并且响应于转换到第二操作模式而将待决命令取消到非易失性存储器。非易失性存储器可以被配置为在经过预定时间段之前完成活动命令。

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