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1. 发明申请

US20190250696A1 POWER SHARING AMONG USER DEVICES 审中-公开
公开(公告)号：US20190250696A1
公开(公告)日：2019-08-15
申请号：US16394081
申请日：2019-04-25
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： James E. BOSTICK , John M. GANCI, JR. , Martin G. KEEN , Sarbajit K. RAKSHIT
IPC分类号： G06F1/3296 , H04W52/02 , G06F1/32 , G06F1/3287 , G06F1/329 , G06Q50/06 , G06Q10/06 , G06F1/3209
CPC分类号： G06F1/3296 , G06F1/32 , G06F1/3209 , G06F1/3287 , G06F1/329 , G06Q10/06 , G06Q50/06 , H04W52/0277 , Y02D10/171 , Y02D10/24 , Y02D70/00 , Y02D70/142
摘要： A method comprises receiving, by a computing device, a desired usage plan for a plurality of user devices associated with a group of users; determining, by the computing device, whether an amount of power available across the plurality of user devices is sufficient to implement the desired usage plan; generating, by the computing device and based on the amount of power available across the plurality of user devices for the desired usage rules, usage rules that allocate the usage of the plurality of the user devices by each user in the group of users; and outputting to the plurality of user devices, the usage rules to cause the plurality of user devices to limit the usage of the plurality of user devices by each user in the group of users based on the allocation.

2. 发明申请

US20180350369A1 Always-On Audio Control for Mobile Device 审中-公开
公开(公告)号：US20180350369A1
公开(公告)日：2018-12-06
申请号：US16101603
申请日：2018-08-13
申请人： Apple Inc.
发明人： Timothy J. Millet , Manu Gulati , Michael F. Culbert
IPC分类号： G10L15/28 , G06F3/16 , G06F1/32 , G10L15/22 , G10L25/48 , G10L15/08
CPC分类号： G10L15/28 , G06F1/32 , G06F1/3228 , G06F1/3287 , G06F3/165 , G10L15/22 , G10L25/48 , G10L2015/088 , Y02D10/171
摘要： In an embodiment, an integrated circuit may include one or more CPUs, a memory controller, and a circuit configured to remain powered on when the rest of the SOC is powered down. The circuit may be configured to receive audio samples from a microphone, and match those audio samples against a predetermined pattern to detect a possible command from a user of the device that includes the SOC. In response to detecting the predetermined pattern, the circuit may cause the memory controller to power up so that audio samples may be stored in the memory to which the memory controller is coupled. The circuit may also cause the CPUs to be powered on and initialized, and the operating system (OS) may boot. During the time that the CPUs are initializing and the OS is booting, the circuit and the memory may be capturing the audio samples.

3. 发明申请

US20180321728A1 REMOTE WAKE-UP OF MOBILE DEVICES 审中-公开
公开(公告)号：US20180321728A1
公开(公告)日：2018-11-08
申请号：US15772026
申请日：2016-10-18
申请人： Displaylink (UK) Limited
发明人： Douglas Morse
IPC分类号： G06F1/32 , H04M1/73 , G06F1/16
CPC分类号： G06F1/3209 , G06F1/1632 , G06F1/3203 , G06F1/3287 , H04M1/73 , Y02D10/171
摘要： A method of controlling a docking station (21) to wake a mobile device (23) from a sleep mode, the mobile device (23) having a data module that is powered off in sleep mode and is capable of transferring data to/from the docking station (21) over a data connection. The mobile device (23) also includes at least one of a power module (211) that is powered on in sleep mode and that is capable of receiving power over a power transfer connection (29b) from a power source (28) in the docking station (21) and a sort-range wireless communication module (46) that is powered on in sleep mode and that is capable of transferring data over a short-range wireless connection (45). The method involves receiving, by the docking station (21) over a Local Area Network, LAN connection, a wake-up message destined for the mobile device (23), generating, by the docking station (21), in response to receiving the wake-up message, a wake-up control signal for transmittal over the power transfer connection (29b) or over the sort-range wireless connection (45) to the mobile device (23), and transmitting the wake-up control signal, from the docking station (21), over the power transfer connection (29b) or over the sort-range wireless connection (45) to the mobile device (23).

4. 发明申请

US20180313673A1 System on a Chip with Always-On Processor 审中-公开
公开(公告)号：US20180313673A1
公开(公告)日：2018-11-01
申请号：US16019087
申请日：2018-06-26
申请人： Apple Inc.
发明人： Brijesh Tripathi , Shane J. Keil , Manu Gulati , Jung Wook Cho , Erik P. Machnicki , Gilbert H. Herbeck , Timothy J. Millet , Joshua P. de Cesare , Anand Dalal
IPC分类号： G01D9/00 , G06F1/32 , G06F13/16
CPC分类号： G01D9/00 , G06F1/3206 , G06F1/3287 , G06F1/3293 , G06F13/1689 , Y02D10/122 , Y02D10/171 , Y02D50/20
摘要： In an embodiment, a system on a chip (SOC) includes a component that remains powered when the remainder of the SOC is powered off. The component may include a sensor capture unit to capture data from various device sensors, and may filter the captured sensor data. Responsive to the filtering, the component may wake up the remainder of the SOC to permit the processing. The component may store programmable configuration data, matching the state at the time the SOC was most recently powered down, for the other components of the SOC, in order to reprogram them after wakeup. In some embodiments, the component may be configured to wake up the memory controller within the SOC and the path to the memory controller, in order to write the data to memory. The remainder of the SOC may remain powered down.

5. 发明申请

US20180299946A1 OPPORTUNISTIC WAKING OF AN APPLICATION PROCESSOR 审中-公开
公开(公告)号：US20180299946A1
公开(公告)日：2018-10-18
申请号：US15952608
申请日：2018-04-13
申请人： Apple Inc.
发明人： Varaprasad V. Lingutla , Cyril De La Cropte De Chanterac
IPC分类号： G06F1/32 , H04W52/02
CPC分类号： G06F1/3296 , G06F1/3206 , G06F1/3287 , G06F1/329 , H04W52/0209 , Y02D10/171 , Y02D10/24 , Y02D70/00 , Y02D70/1242 , Y02D70/1262 , Y02D70/142 , Y02D70/144 , Y02D70/164 , Y02D70/166 , Y02D70/24 , Y02D70/26
摘要： Described herein in various embodiments are techniques to better coordinate long wakeup events on a network processor that are due to radio or network activity with the long wakeups that are due to requests from an application processor. In one embodiment, power management logic can receive wake requests from system processes upon notice that one or more application processors are transitioning into a low power state. The power management logic can coalesce the wake requests based on a supplied margin and determine a wake timeframe in which the application processor may be opportunistically woken from the low power state. The power management logic can provide the wake timeframe for the application processor to a network processor in the system. The network processor can opportunistically cause an early wake of the application processor during the wake timeframe.

6. 发明申请

US20180275993A1 POWER MANAGEMENT OF BRANCH PREDICTORS IN A COMPUTER PROCESSOR 审中-公开
公开(公告)号：US20180275993A1
公开(公告)日：2018-09-27
申请号：US15995682
申请日：2018-06-01
申请人： International Business Machines Corporation
发明人： DAVID S. LEVITAN , NICHOLAS R. ORZOL , ROBERT A. PHILHOWER
IPC分类号： G06F9/38 , G06F1/32
CPC分类号： G06F9/3848 , G06F1/3237 , G06F1/3243 , G06F1/3246 , G06F1/3287 , G06F9/30058 , G06F9/30083 , G06F9/3806 , G06F9/3808 , G06F9/3842 , G06F9/3844 , G06F9/3846 , Y02D10/152 , Y02D10/171
摘要： A computer processor includes a branch prediction unit that includes a local branch predictor and a global branch predictor. Managing power consumption in such a computer processor includes, for each of a plurality of branch instructions: performing, by the local branch predictor, a local branch prediction; performing, by each of the global branch predictors, a global branch prediction; determining to utilize the local branch prediction over the global branch predictions as a branch prediction for the branch instruction; incrementing a value of a counter; determining whether the value of the counter exceeds a predetermined threshold; and if the value of the counter exceeds the predetermined threshold, powering down at least one of the global branch predictors and configuring the branch prediction unit to bypass the powered down global branch predictor for branch predictions of subsequent branch instructions.

7. 发明申请

US20180260153A1 METHOD, APPARATUS, AND SYSTEM FOR ENERGY EFFICIENCY AND ENERGY CONSERVATION INCLUDING AUTONOMOUS HARDWARE-BASED DEEP POWER DOWN IN DEVICES 审中-公开
公开(公告)号：US20180260153A1
公开(公告)日：2018-09-13
申请号：US15786424
申请日：2017-10-17
申请人： Intel Corporation
发明人： Inder M. Sodhi , Alon Naveh , Doron Rajwan , Ryan D. Wells , Eric C. Samson
IPC分类号： G06F3/06 , G06F1/32
CPC分类号： G06F3/0625 , G06F1/3206 , G06F1/3278 , G06F1/3287 , G06F3/0634 , G06F3/0673 , Y02D10/157 , Y02D10/171
摘要： Embodiments of systems, apparatuses, and methods for energy efficiency and energy conservation including enabling autonomous hardware-based deep power down of devices are described. In one embodiment, a system includes a device, a static memory, and a power control unit coupled with the device and the static memory. The system further includes a deep power down logic of the power control unit to monitor a status of the device, and to transfer the device to a deep power down state when the device is idle. In the system, the device consumes less power when in the deep power down state than in the idle state.

8. 发明授权

US10061282B2 Function control device, apparatus including same, and communication establishing method 有权
公开(公告)号：US10061282B2
公开(公告)日：2018-08-28
申请号：US14948493
申请日：2015-11-23
申请人： Yoshimichi Kanda
发明人： Yoshimichi Kanda
IPC分类号： G05B11/01 , G05B19/042 , G06F1/32 , G06K15/00 , H04N1/00
CPC分类号： G05B19/042 , G05B2219/2214 , G06F1/3209 , G06F1/3287 , G06F1/3293 , G06K15/4055 , H04N1/00896 , H04N2201/0094 , Y02D10/122 , Y02D10/171
摘要： An apparatus includes a function control device to provide a specific function to the apparatus, a network control device to control communication between the apparatus and other apparatus via a network, and a main control device to control operation of the apparatus. The network control device operates while communication with the function control device is being cut off when the function control device is not supplied with power, The function control device includes a user circuit to detect restarting of a power supply to the function control device, and establish communication with the network control device in response to detection of restarting of the power supply to the function control device. The main control device controls communication between the apparatus and the other apparatus, through communication established between the main control device and the function control device and communication established between the function control device and the network control device.

9. 发明授权

US10055002B2 System and method for energy efficient power saving on multifunction devices 有权
公开(公告)号：US10055002B2
公开(公告)日：2018-08-21
申请号：US15134140
申请日：2016-04-20
申请人： Kabushiki Kaisha Toshiba , Toshiba TEC Kabushiki Kaisha
发明人： Jia Zhang , Michael L. Yeung
IPC分类号： G06F1/00 , G06F1/32 , H04L12/26
CPC分类号： G06F1/3284 , G06F1/3215 , G06F1/3287 , G06F3/1221 , G06F3/1229 , G06F3/126 , G06F3/1288 , H04L43/08 , Y02D10/159 , Y02D10/1592 , Y02D10/171 , Y02D50/20
摘要： A document processing system includes a power scheduling server configured to receive time-based usage data from a multifunction device. In response to receiving the usage data from the multifunction device, the power scheduling server analyzes the usage data and determines a power saving policy for the multifunction device. The power scheduling server transmits the power saving policy to the multifunction device. The multifunction device performs changes of operational state based on usage and in accordance with the received power saving policy.

10. 发明申请

US20180224921A1 Clock Glitch Prevention for Retention Operational Mode 审中-公开
公开(公告)号：US20180224921A1
公开(公告)日：2018-08-09
申请号：US15425980
申请日：2017-02-06
申请人： QUALCOMM Incorporated
发明人： Harshat Pant , Ramaprasath Vilangudipitchai , Srijith Nair , Mohammad Tamjidi
IPC分类号： G06F1/32
CPC分类号： G06F1/3287 , G06F1/10 , G06F1/3296 , H03K5/13 , Y02D10/171
摘要： An integrated circuit (IC) is disclosed with clock glitch prevention for a retention operational mode. In an example aspect, the IC includes a clock signal source that generates a source value for a clock signal, which is distributed by a clock tree along a downstream direction. The IC further includes a deviant clock signal generator, a clock signal controller, and a retention storage device. The deviant clock signal generator is disposed along the clock tree downstream from the clock signal source and generates a deviant value for the clock signal. The clock signal controller prevents downstream propagation of the deviant value of the clock signal responsive to a retention signal. The retention storage device is disposed downstream from the clock signal controller. The retention storage device processes data responsive to the clock signal and retains a data value during a power collapse event responsive to the retention signal.

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