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31. 发明授权

US10447597B1 Path and latency tracking 有权
公开(公告)号：US10447597B1
公开(公告)日：2019-10-15
申请号：US15600751
申请日：2017-05-21
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Jeongkeun Lee , Parag Bhide , Jithin Thomas , Xiaozhou Li , Georgios Nikolaidis
IPC分类号： H04L12/801 , H04L12/24 , H04L12/26 , H04L29/12
摘要： Some embodiments of the invention provide a path-and-latency tracking (PLT) method. At a forwarding element, this method in some embodiments detects the path traversed by a data message through a set of forwarding elements, and the latency that the data message experiences at each of the forwarding elements in the path. In some embodiments, the method has a forwarding element in the path insert its forwarding element identifier and path latency in a header of the data message that it forwards. The method of some embodiments also uses fast PLT operators in the data plane of the forwarding elements to detect new data message flows, to gather PLT data from these data message flows, and to detect path or latency changes for previously detected data message flows. In some embodiments, the method then uses control plane processes (e.g., of the forwarding elements or other devices) to collect and analyze the PLT data gathered in the data plane from new or existing flows.

32. 发明授权

US10305820B1 Network forwarding element with key-value processing in the data plane 有权
公开(公告)号：US10305820B1
公开(公告)日：2019-05-28
申请号：US15730700
申请日：2017-10-11
申请人： Barefoot Networks, Inc.
发明人： Xiaozhou Li , Jeongkeun Lee , Changhoon Kim , John Nathan Foster
IPC分类号： H04L12/935 , H04L12/747 , H04L12/741
摘要： Some embodiments of the invention provide a forwarding element that has one or more data plane, message-processing pipelines with key-value processing circuits. The forwarding element's data plane key-value circuits allow the forwarding element to perform key-value services that would otherwise have to be performed by data compute nodes connected by the network fabric that includes the forwarding element. In some embodiments, the key-value (KV) services of the forwarding element and other similar forwarding elements supplement the key-value services of a distributed set of key-value servers by caching a subset of the most commonly used key-value pairs in the forwarding elements that connect the set of key-value servers with their client applications. In some embodiments, the key-value circuits of the forwarding element perform the key-value service operations at message-processing line rates at which the forwarding element forwards messages to the data compute nodes and/or to other network forwarding elements.

33. 发明授权

US10268634B1 Proxy hash table 有权
公开(公告)号：US10268634B1
公开(公告)日：2019-04-23
申请号：US15365887
申请日：2016-11-30
申请人： Barefoot Networks, Inc.
发明人： Patrick Bosshart , Changhoon Kim
IPC分类号： G06F3/06 , G06F16/22 , G06F12/00
摘要： Some embodiments of the invention provide novel methods for storing data in a hash-addressed memory and retrieving stored data from the hash-addressed memory. In some embodiments, the method receives a search key and a data tuple. The method then uses a first hash function to generate a first hash value from the search key, and then uses this first hash value to identify an address in the hash-addressed memory. The method also uses a second hash function to generate a second hash value, and then stores this second hash value along with the data tuple in the memory at the address specified by the first hash value. To retrieve data from the hash-addressed memory, the method of some embodiments receives a search key. The method then uses the first hash function to generate a first hash value from the search key, and then uses this first hash value to identify an address in the hash-addressed memory. At the identified address, the hash-addressed memory stores a second hash value and a data tuple. The method retrieves a second hash value from the memory at the identified address, and compares this second hash value with a third hash value that the method generates from the search key by using the second hash function. When the second and third hash values match, the method retrieves the data tuple that the memory stores at the identified address.

34. 发明授权

US10075567B1 Packet generation in the data plane of a forwarding element 有权
公开(公告)号：US10075567B1
公开(公告)日：2018-09-11
申请号：US15167552
申请日：2016-05-27
申请人： Barefoot Networks, Inc.
发明人： Steven Licking , Chaitanya Kodeboyina , Julianne Zhu , Changhoon Kim
IPC分类号： H04L12/54 , H04L29/06 , H04L12/741
CPC分类号： H04L69/22 , H04L43/08 , H04L43/0811 , H04L43/10 , H04L45/28 , H04L45/74 , H04L45/7453 , H04L49/3063
摘要： A method of generating packets in the data plane of a forwarding element is provided. The method selects a configuration set from a plurality of configuration sets of based on a triggering event. The method generates a set of packets using a packet template that corresponds to the selected configuration set. The method sets values of a plurality of the packet fields to identify different information such as the destination of packets. The method places the generated set of packets into an ingress pipeline of the forwarding element.

35. 发明授权

US10063479B2 Fast adjusting load balancer 有权
公开(公告)号：US10063479B2
公开(公告)日：2018-08-28
申请号：US14507814
申请日：2014-10-06
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Patrick Bosshart
IPC分类号： H04J1/16 , H04L12/803 , H04L12/931 , H04L12/933 , H04L12/743 , H04L29/12
CPC分类号： H04L47/125 , H04L45/7453 , H04L49/10 , H04L49/354 , H04L61/20 , H04L61/2521
摘要： Some embodiments of the invention provide a load balancer for distributing packet flows that are addressed to a group of data compute nodes (DCNs) amongst the DCNs of the group. In some embodiments, the load balancer includes a connection data storage comprising several different destination network address translation (DNAT) tables. Each particular DNAT table is defined at a particular instance in time and stores the identity of a plurality DCNs that are part of the group at the particular instance in time. Each time a DCN is added to the group, the load balancer of some embodiments creates a new DNAT table in the connection data storage for processing new packet flows, while using previously created DNAT tables to process packets that are part of previously processed packet flows.

36. 发明申请

US20180234340A1 DATA-PLANE STATEFUL PROCESSING UNITS IN PACKET PROCESSING PIPELINES 审中-公开
公开(公告)号：US20180234340A1
公开(公告)日：2018-08-16
申请号：US15888054
申请日：2018-02-04
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Steven Licking , Anirudh Sivaraman Kaushalram , Chaitanya Kodeboyina
IPC分类号： H04L12/741 , H04L29/06
摘要： A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

37. 发明授权

US09912610B2 Data-plane stateful processing units in packet processing pipelines 有权
公开(公告)号：US09912610B2
公开(公告)日：2018-03-06
申请号：US14863961
申请日：2015-09-24
申请人： Barefoot Networks, Inc.
发明人： Patrick Bosshart , Jay Evan Scott Peterson , Michael Gregory Ferrara , Changhoon Kim , Steven Licking , Chaitanya Kodeboyina
IPC分类号： H04L12/931 , H04L12/00 , H04L12/26
CPC分类号： H04L49/00 , H04L12/00 , H04L43/0864
摘要： A synchronous packet-processing pipeline whose data paths are populated with data-plane stateful processing units (DSPUs) is provided. A DSPU is a programmable processor whose operations are synchronous with the dataflow of the packet-processing pipeline. A DSPU performs every computation with fixed latency. Each DSPU is capable of maintaining a set of states and perform its computations based on its maintained set of states. The programming of a DSPU determines how and when the DSPU updates one of its maintained states. Such programming may configure the DSPU to update the state based on its received packet data, or to change the state regardless of the received packet data.

38. 发明授权

US11349781B1 Recording in an external memory data messages processed by a data plane circuit 有权
公开(公告)号：US11349781B1
公开(公告)日：2022-05-31
申请号：US16540773
申请日：2019-08-14
申请人： Barefoot Networks, Inc.
发明人： Antonin Mathieu Bas , Anurag Agrawal , Changhoon Kim
IPC分类号： H04L12/28 , H04L49/00 , H04L45/745 , H04L49/9057 , H04L45/00
摘要： Some embodiments provide novel circuits for recording data messages received by a data plane circuit of a forwarding element in an external memory outside of the data plane circuit. The external memory in some embodiments is outside of the forwarding element. In some embodiments, the data plane circuit encapsulates the received data messages that should be recorded with encapsulation headers, inserts into these headers addresses that identify locations for storing these data messages in a memory external to the data plane circuit, and forwards these encapsulated data messages so that these messages can be stored in the external memory by another circuit. Instead of encapsulating received data messages for storage, the data plane circuit in some embodiments encapsulates copies of the received data messages for storage. Accordingly, in these embodiments, the data plane circuit makes copies of the data messages that it needs to record.

39. 发明授权

US11258685B1 Packet generation-based bidirectional forwarding detection 有权
公开(公告)号：US11258685B1
公开(公告)日：2022-02-22
申请号：US16024908
申请日：2018-07-01
申请人： Barefoot Networks, Inc.
发明人： Steven Licking , Chaitanya Kodeboyina , Julianne Zhu , Changhoon Kim
IPC分类号： H04L12/26 , H04L43/08 , H04L45/7453 , H04L43/16 , H04L49/00
摘要： A method of performing bidirectional forwarding detection (BFD) by a hardware forwarding element that includes a set of ingress pipelines and a set of egress pipelines. Each ingress pipeline includes a packet generator. A packet generator in a first pipeline periodically generates a pair of packets to monitor the health of a particular egress link. The pair includes a BFD transmit packet and a BFD dummy transmit packet. The method forwards each dummy BFD transmit packet to a first egress pipeline and increments a counter at the first egress pipeline. Each BFD packet is transmitted through the particular egress link to a network node. BFD packets received from the network node are forwarded to the first egress pipeline and the value of the counter is rest. The method marks the particular egress link as failed when the value of the counter exceeds a predetermined threshold.

40. 发明授权

US11151073B1 Augmenting data plane functionality with field programmable integrated circuits 有权
公开(公告)号：US11151073B1
公开(公告)日：2021-10-19
申请号：US16540766
申请日：2019-08-14
申请人： Barefoot Networks, Inc.
发明人： Antonin Mathieu Bas , Anurag Agrawal , Changhoon Kim
IPC分类号： G06F13/42 , H03K19/173 , G06F13/16
摘要： Some embodiments use one or more FPGAs and external memories associated with the FPGAs to implement large, hash-addressable tables for a data plane circuit. These embodiments configure at least one message processing stage of the DP circuit to store (1) a first plurality of records for matching with a set of data messages received by the DP circuit, and (2) a redirection record redirecting data messages that do not match the first plurality of records to a DP egress port associated with the memory circuit. These embodiments configure an external memory circuit to store a larger, second set of records for matching with redirected data messages received through the DP egress port associated with the memory circuit. This external memory circuit is a hash-addressable memory in some embodiments. To determine whether a redirected data message matches a record in the second set of record, the method of some embodiments configures an FPGA associated with the hash-addressable external memory to use a collision free hash process to generate a collision-free, hash address value from a set of attributes of the data message. This hash address value specifies an address in the external memory for the record in the second set of records to compare with the redirected data message.

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