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1. 发明授权

US11546273B2 Forwarding element data plane with computing parameter distributor 有权
公开(公告)号：US11546273B2
公开(公告)日：2023-01-03
申请号：US16945012
申请日：2020-07-31
申请人： Barefoot Networks, Inc.
发明人： Masoud Moshref Javadi , Changhoon Kim , Patrick W. Bosshart , Anurag Agrawal
IPC分类号： H04L12/935 , H04L49/00 , G06F9/455 , G06N3/08
摘要： Some embodiments provide a network forwarding element with a data-plane forwarding circuit that has a parameter collecting circuit to store and distribute parameter values computed by several machines in a network. In some embodiments, the machines perform distributed computing operations, and the parameter values that compute are parameter values associated with the distributed computing operations. The parameter collecting circuit of the data-plane forwarding circuit (data plane) in some embodiments (1) stores a set of parameter values computed and sent by a first set of machines, and (2) distributes the collected parameter values to a second set of machines once it has collected the set of parameter values from all the machines in the first set. The first and second sets of machines are the same set of machines in some embodiments, while they are different sets of machines (e.g., one set has at least one machine that is not in the other set) in other embodiments. In some embodiments, the parameter collecting circuit performs computations on the parameter values that it collects and distributes the result of the computations once it has processed all the parameter values distributed by the first set of machines. The computations are aggregating operations (e.g., adding, averaging, etc.) that combine corresponding subset of parameter values distributed by the first set of machines.

2. 发明申请

US20220353204A1 MESSAGING BETWEEN REMOTE CONTROLLER AND FORWARDING ELEMENT 有权
公开(公告)号：US20220353204A1
公开(公告)日：2022-11-03
申请号：US17867508
申请日：2022-07-18
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Xiaozhou Li , Anurag Agrawal , Julianne Zhu
IPC分类号： H04L49/90 , H03M13/09 , H04L45/7453 , H04L41/08 , H04L41/0803 , H04L49/00 , H04L49/10 , H04L69/22
摘要： Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

3. 发明授权

US11456970B1 Augmenting data plane functionality with field programmable integrated circuits 有权
公开(公告)号：US11456970B1
公开(公告)日：2022-09-27
申请号：US16540741
申请日：2019-08-14
申请人： Barefoot Networks, Inc.
发明人： Antonin Mathieu Bas , Anurag Agrawal , Changhoon Kim
IPC分类号： H04L49/90 , H04L47/50 , H04L49/40 , H04L49/104 , H04L43/50
摘要： Some embodiments provide novel circuits for augmenting the functionality of a data plane circuit of a forwarding element with one or more field programmable circuits and external memory circuits. The external memories in some embodiments serve as deep buffers that receive through one or more FPGAs a set of data messages from the data plane (DP) circuit to store temporarily. In some of these embodiments, one or more of the FPGAs implement schedulers that specify when data messages should be retrieved from the external memories and provided back to the data plane circuit for forwarding through the network. For instance, in some embodiments, a particular FPGA can perform a scheduling operation for a first set of data messages stored in its associated external memory, and can direct another FPGA to perform the scheduling operation for a second set of data messages stored in the particular FPGA's associated external memory. Specifically, in these embodiments, the particular FPGA determines when the first subset of data messages stored in its associated external memory should be forwarded back to the data plane circuit to forward to data messages in the network, while directing another FPGA to determine when a second subset of data messages stored in the particular FPGA's external memory should be forwarded back to the data plane circuit.

4. 发明授权

US11425038B2 Packet header field extraction 有权
公开(公告)号：US11425038B2
公开(公告)日：2022-08-23
申请号：US16695044
申请日：2019-11-25
申请人： Barefoot Networks, Inc.
发明人： Patrick Bosshart
IPC分类号： H04L12/741 , H04L12/933 , H04L45/745 , H04L45/00 , H04L49/101 , H04L45/64 , H04L49/1546 , H04L69/22 , H04L45/74 , H04L45/42
摘要： Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

5. 发明授权

US11411870B2 Packet header field extraction 有权
公开(公告)号：US11411870B2
公开(公告)日：2022-08-09
申请号：US16573847
申请日：2019-09-17
申请人： Barefoot Networks, Inc.
发明人： Patrick Bosshart
IPC分类号： H04L12/741 , H04L12/933 , H04L45/745 , H04L45/00 , H04L49/101 , H04L45/64 , H04L49/1546 , H04L69/22 , H04L45/74 , H04L45/42
摘要： Some embodiments provide a method for processing a packet for a pipeline of a hardware switch. The pipeline, in some embodiments, includes several different stages that match against packet header fields and modify packet header fields. The method receives a packet that includes a set of packet headers. The method then populates, for each packet header in the set of packet headers, (i) a first set of registers with packet header field values of the packet header that are used in the pipeline, and (ii) a second set of registers with packet header field values of the packet header that are not used in the pipeline.

6. 发明申请

US20220083352A1 DATA PLANE PROGRAM VERIFICATION 有权
公开(公告)号：US20220083352A1
公开(公告)日：2022-03-17
申请号：US17537301
申请日：2021-11-29
申请人： Barefoot Networks, Inc.
发明人： Jeongkeun LEE , Cole Nathan Schlesinger , John Nathan FOSTER , Han Wang , Robert SOULE , William Hallahan , Steffen Julif Smolka , Mon Jed LIU
IPC分类号： G06F9/445 , G06F11/36 , G06F8/51 , H04L12/741
摘要： A method for verifying data plane programs is provided in some embodiments. Because the behavior of a data plane program (e.g., a program written in the P4 language) is determined in part by the control plane populating match-action tables with specific forwarding rules, in some embodiments, programmers are provided with a way to document assumptions about the control plane using annotations (e.g., in the form of “assertions” or “assumptions” about the state based on the unknown control plane contribution). In some embodiments, annotations are added automatically to verify common properties, including checking that every header read or written is valid, that every expression has a well-defined value, and that all standard metadata is manipulated correctly. The method in some embodiments translates programs from a first language (e.g., P4) to a second language (e.g., Guarded Command Language (GCL)) for verification by a satisfiability modulo theory (SMT) solver.

7. 发明授权

US11258703B1 Data plane for learning flows, collecting metadata regarding learned flows and exporting metadata regarding learned flows 有权
公开(公告)号：US11258703B1
公开(公告)日：2022-02-22
申请号：US15927859
申请日：2018-03-21
申请人： Barefoot Networks, Inc.
发明人： Steven Licking , Jeongkeun Lee , Patrick Bosshart , Anurag Agrawal , Michael Gregory Ferrara , Jay Evan Scott Peterson
IPC分类号： H04L12/721 , H04L12/801 , H04L12/851 , H04L12/751 , H04L45/00 , H04L47/11 , H04L47/2483 , H04L41/22
摘要： Some embodiments provide a data-plane forwarding circuit that can be configured to learn about a new message flow and to maintain metadata about the new message flow without first having a control plane first configure the data plane to maintain metadata about the flow. To perform its forwarding operations, the data plane includes several data message processing stages that are configured to process the data tuples associated with the data messages received by the data plane. In some embodiments, parts of the data plane message-processing stages are also configured to operate as a flow-tracking circuit that includes (1) a flow-identifying circuit to identify message flows received by the data plane, and (2) a first set of storages to store metadata about the identified flows.

8. 发明授权

US11223520B1 Remote control plane directing data plane configurator 有权
公开(公告)号：US11223520B1
公开(公告)日：2022-01-11
申请号：US15784191
申请日：2017-10-16
申请人： Barefoot Networks, Inc.
发明人： Changhoon Kim , Xiaozhou Li , Anurag Agrawal , Julianne Zhu
IPC分类号： H04L1/00 , H04L12/24 , H04L12/743 , H04L12/933 , H04L29/06 , H04L12/935
摘要： Some embodiments of the invention provide a forwarding element that can be configured through in-band data-plane messages from a remote controller that is a physically separate machine from the forwarding element. The forwarding element of some embodiments has data plane circuits that include several configurable message-processing stages, several storage queues, and a data-plane configurator. A set of one or more message-processing stages of the data plane are configured (1) to process configuration messages received by the data plane from the remote controller and (2) to store the configuration messages in a set of one or more storage queues. The data-plane configurator receives the configuration messages stored in the set of storage queues and configures one or more of the configurable message-processing stages based on configuration data in the configuration messages.

9. 发明申请

US20210399998A1 AUGMENTING DATA PLANE FUNCTIONALITY WITH FIELD PROGRAMMABLE INTEGRATED CIRCUITS 有权
公开(公告)号：US20210399998A1
公开(公告)日：2021-12-23
申请号：US17466715
申请日：2021-09-03
申请人： Barefoot Networks, Inc.
发明人： Antonin Mathieu BAS , Anurag AGRAWAL , Changhoon KIM
IPC分类号： H04L12/879
摘要： Some embodiments use one or more FPGAs and external memories associated with the FPGAs to implement large, hash-addressable tables for a data plane circuit. These embodiments configure at least one message processing stage of the DP circuit to store (1) a first plurality of records for matching with a set of data messages received by the DP circuit, and (2) a redirection record redirecting data messages that do not match the first plurality of records to a DP egress port associated with the memory circuit. These embodiments configure an external memory circuit to store a larger, second set of records for matching with redirected data messages received through the DP egress port associated with the memory circuit. This external memory circuit is a hash-addressable memory in some embodiments. To determine whether a redirected data message matches a record in the second set of record, the method of some embodiments configures an FPGA associated with the hash-addressable external memory to use a collision free hash process to generate a collision-free, hash address value from a set of attributes of the data message. This hash address value specifies an address in the external memory for the record in the second set of records to compare with the redirected data message.

10. 发明授权

US10911377B1 Using stateful traffic management data to perform packet processing 有权
公开(公告)号：US10911377B1
公开(公告)日：2021-02-02
申请号：US15835238
申请日：2017-12-07
申请人： Barefoot Networks, Inc.
发明人： Yi Li , Michael Feng , Anurag Agrawal , Jeongkeun Lee , Changhoon Kim , Remy Chang
IPC分类号： H04L12/935 , H04L12/863 , H04L12/823 , H04L12/933 , H04L12/709
摘要： Some embodiments provide a method for an ingress packet processing pipeline of a network forwarding integrated circuit (IC). The ingress packet processing pipeline is for receiving packets from a port of the network forwarding IC and processing the packets to assign different packets to different queues of a traffic management unit of the network forwarding IC. The method receives state data from the traffic management unit. The method stores the state data in a stateful table. The method assigns a particular packet to a particular queue based on the state data received from the traffic management unit and stored in the stateful table.

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