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31. 发明申请

US20220261948A1 COMPUTE OPTIMIZATION MECHANISM 有权
公开(公告)号：US20220261948A1
公开(公告)日：2022-08-18
申请号：US17684187
申请日：2022-03-01
申请人： Intel Corporation
发明人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. Macpherson , John C. Weast , Feng Chen , Farshad Akhbari , Narayan Srinivasa , Nadathur Rajagopalan Satish , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman
IPC分类号： G06T1/20 , G06F3/14 , G06F9/30 , G06F9/38 , G06N3/04 , G06N3/063 , G06N3/08 , G06T15/00 , G09G5/36
摘要： An apparatus to facilitate compute optimization is disclosed. The apparatus includes a mixed precision core including mixed-precision execution circuitry to execute one or more of the mixed-precision instructions to perform a mixed-precision dot-product operation comprising to perform a set of multiply and accumulate operations.

32. 发明授权

US10748237B2 Adaptive scheduling for task assignment among heterogeneous processor cores 有权
公开(公告)号：US10748237B2
公开(公告)日：2020-08-18
申请号：US16185965
申请日：2018-11-09
申请人： Intel Corporation
发明人： Rajkishore Barik , Tatiana Shpeisman , Brian T. Lewis , Rashid Kaleem
IPC分类号： G06T1/20 , G09G5/00 , G06F3/14 , G09G5/36
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for adaptive scheduling of task assignment among heterogeneous processor cores. The system may include any number of CPUs, a graphics processing unit (GPU) and memory configured to store a pool of work items to be shared by the CPUs and GPU. The system may also include a GPU proxy profiling module associated with one of the CPUs to profile execution of a first portion of the work items on the GPU. The system may further include profiling modules, each associated with one of the CPUs, to profile execution of a second portion of the work items on each of the CPUs. The measured profiling information from the CPU profiling modules and the GPU proxy profiling module is used to calculate a distribution ratio for execution of a remaining portion of the work items between the CPUs and the GPU.

33. 发明授权

US10255122B2 Function callback mechanism between a Central Processing Unit (CPU) and an auxiliary processor 有权
公开(公告)号：US10255122B2
公开(公告)日：2019-04-09
申请号：US15537357
申请日：2015-11-24
申请人： Intel Corporation
发明人： Brian T. Lewis , Rajkishore Barik , Tatiana Shpeisman
IPC分类号： G06F9/46 , G06F9/54 , G06T1/20
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.

34. 发明申请

US20180307971A1 DYNAMIC PRECISION FOR NEURAL NETWORK COMPUTE OPERATIONS 审中-公开
公开(公告)号：US20180307971A1
公开(公告)日：2018-10-25
申请号：US15495020
申请日：2017-04-24
申请人： Intel Corporation
发明人： Kamal Sinha , Balaji Vembu , Eriko Nurvitadhi , Nicolas C. Galoppo Von Borries , Rajkishore Barik , Tsung-Han Lin , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Anbang Yao , Tatiana Shpeisman , Abhishek R. Appu , Altug Koker , Farshad Akhbari , Narayan Srinivasa , Feng Chen , Dukhwan Kim , Nadathur Rajagopalan Satish , John C. Weast , Mike B. MacPherson , Linda L. Hurd , Vasanth Ranganathan , Sanjeev S. Jahagirdar
IPC分类号： G06N3/063 , G06N3/08 , G06N3/04 , G06T1/20
CPC分类号： G06N3/063 , G06F1/3287 , G06F1/3293 , G06F9/30014 , G06F9/30036 , G06F15/78 , G06N3/04 , G06N3/08 , G06T1/20 , G06T1/60 , G06T15/005
摘要： In an example, an apparatus comprises a compute engine comprising a high precision component and a low precision component; and logic, at least partially including hardware logic, to receive instructions in the compute engine; select at least one of the high precision component or the low precision component to execute the instructions; and apply a gate to at least one of the high precision component or the low precision component to execute the instructions. Other embodiments are also disclosed and claimed.

35. 发明申请

US20180293205A1 GRAPHICS PROCESSING INTEGRATED CIRCUIT PACKAGE 审中-公开
公开(公告)号：US20180293205A1
公开(公告)日：2018-10-11
申请号：US15482796
申请日：2017-04-09
申请人： Intel Corporation
发明人： Altug Koker , Farshad Akhbari , Feng Chen , Dukhwan Kim , Narayan Srinivasa , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Joydeep Ray , Ping T. Tang , Michael Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu
IPC分类号： G06F15/80 , G06F9/30 , G06F9/38 , G06F13/40 , G11C5/02
CPC分类号： G06F15/8007 , G06F9/3004 , G06F13/00 , G06F13/4027 , G06N3/0445 , G06N3/0454 , G06N3/0481 , G06N3/063 , G06N3/084 , G06T1/20
摘要： An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

36. 发明申请

US20170109213A1 WORK STEALING IN HETEROGENEOUS COMPUTING SYSTEMS 审中-公开
公开(公告)号：US20170109213A1
公开(公告)日：2017-04-20
申请号：US15391549
申请日：2016-12-27
申请人： Intel Corporation
发明人： Rajkishore Barik , Stephan A. Herhut , Jaswanth Sreeram , Tatiana Shpeisman , Richard L. Hudson
IPC分类号： G06F9/50
CPC分类号： G06F9/5083 , G06F9/505 , G06F13/4239
摘要： A work stealer apparatus includes a determination module. The determination module is to determine to steal work from a first hardware computation unit of a first type for a second hardware computation unit of a second type that is different than the first type. The work is to be queued in a first work queue, which is to correspond to the first hardware computation unit, and which is to be stored in a shared memory that is to be shared by the first and second hardware computation units. A synchronized work stealer module is to steal the work through a synchronized memory access to the first work queue. The synchronized memory access is to be synchronized relative to memory accesses to the first work queue from the first hardware computation unit.

37. 发明授权

US09342384B1 Function callback mechanism between a central processing unit (CPU) and an auxiliary processor 有权
标题翻译：中央处理单元（CPU）和辅助处理器之间的功能回调机制
公开(公告)号：US09342384B1
公开(公告)日：2016-05-17
申请号：US14574545
申请日：2014-12-18
申请人： Intel Corporation
发明人： Brian T. Lewis , Rajkishore Barik , Tatiana Shpeisman
IPC分类号： G06F13/00 , G06F9/54 , G06T1/20
CPC分类号： G06F9/544 , G06T1/20
摘要： Generally, this disclosure provides systems, devices, methods and computer readable media for implementing function callback requests between a first processor (e.g., a GPU) and a second processor (e.g., a CPU). The system may include a shared virtual memory (SVM) coupled to the first and second processors, the SVM configured to store at least one double-ended queue (Deque). An execution unit (EU) of the first processor may be associated with a first of the Deques and configured to push the callback requests to that first Deque. A request handler thread executing on the second processor may be configured to: pop one of the callback requests from the first Deque; execute a function specified by the popped callback request; and generate a completion signal to the EU in response to completion of the function.
摘要翻译：通常，本公开提供了用于在第一处理器（例如，GPU）和第二处理器（例如，CPU）之间实现功能回调请求的系统，设备，方法和计算机可读介质。该系统可以包括耦合到第一和第二处理器的共享虚拟存储器（SVM），所述SVM被配置为存储至少一个双端队列（Deque）。第一处理器的执行单元（EU）可以与第一个Deques相关联，并被配置为将回调请求推送到第一个Deque。在第二处理器上执行的请求处理程序线程可以被配置为：从第一Deque弹出一个回调请求; 执行弹出的回调请求指定的功能; 并响应功能的完成向EU产生完成信号。

38. 发明申请

US20230039729A1 AUTONOMOUS VEHICLE NEURAL NETWORK OPTIMIZATION 有权
公开(公告)号：US20230039729A1
公开(公告)日：2023-02-09
申请号：US17963539
申请日：2022-10-11
申请人： Intel Corporation
发明人： Abhishek R. Appu , Altug Koker , Linda L. Hurd , Dukhwan Kim , Mike B. MacPherson , John C. Weast , Justin E. Gottschlich , Jingyi Jin , Barath Lakshmanan , Chandrasekaran Sakthivel , Michael S. Strickland , Joydeep Ray , Kamal Sinha , Prasoonkumar Surti , Balaji Vembu , Ping T. Tang , Anbang Yao , Tatiana Shpeisman , Xiaoming Chen
IPC分类号： G05B13/02 , G05D1/00 , G06N3/04 , G06N3/02 , G06N5/04 , G06N20/00
摘要： Methods and apparatus relating to autonomous vehicle neural network optimization techniques are described. In an embodiment, the difference between a first training dataset to be used for a neural network and a second training dataset to be used for the neural network is detected. The second training dataset is authenticated in response to the detection of the difference. The neural network is used to assist in an autonomous vehicle/driving. Other embodiments are also disclosed and claimed.

39. 发明申请

US20230027203A1 GRAPHICS PROCESSING INTEGRATED CIRCUIT PACKAGE 有权
公开(公告)号：US20230027203A1
公开(公告)日：2023-01-26
申请号：US17826674
申请日：2022-05-27
申请人： Intel Corporation
发明人： Altug Koker , Farshad Akhbari , Feng Chen , Dukhwan Kim , Narayan Srinivasa , Nadathur Rajagopalan Satish , Liwei Ma , Jeremy Bottleson , Eriko Nurvitadhi , Joydeep Ray , Ping T. Tang , Michael S. Strickland , Xiaoming Chen , Tatiana Shpeisman , Abhishek R. Appu
IPC分类号： G06F15/80 , G06F13/40 , G06T1/20 , G06F9/30 , G06F13/00 , G06N3/04 , G06N3/063 , G06N3/08
摘要： An integrated circuit (IC) package apparatus is disclosed. The IC package includes one or more processing units and a bridge, mounted below the one or more processing unit, including one or more arithmetic logic units (ALUs) to perform atomic operations.

40. 发明授权

US11461107B2 Compute unit having independent data paths 有权
公开(公告)号：US11461107B2
公开(公告)日：2022-10-04
申请号：US16227645
申请日：2018-12-20
申请人： Intel Corporation
发明人： Elmoustapha Ould-Ahmed-Vall , Barath Lakshmanan , Tatiana Shpeisman , Joydeep Ray , Ping T. Tang , Michael Strickland , Xiaoming Chen , Anbang Yao , Ben J. Ashbaugh , Linda L. Hurd , Liwei Ma
IPC分类号： G06F9/38 , G06F9/30 , G06F15/80 , G06F13/42 , G06F13/40 , G06N20/00 , G06T1/20 , G06N3/04 , G06N3/063 , G06N3/08 , G06N20/10 , G06F9/50 , G06N3/00
摘要： One embodiment provides for a general-purpose graphics processing unit comprising a streaming multiprocessor having a single instruction, multiple thread (SIMT) architecture including hardware multithreading. The streaming multiprocessor comprises multiple processing blocks including multiple processing cores. The processing cores include independent integer and floating-point data paths that are configurable to concurrently execute multiple independent instructions. A memory is coupled with the multiple processing blocks.

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