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31. 发明授权

US09305938B2 Methods of fabricating integrated structures, and methods of forming vertically-stacked memory cells 有权
标题翻译：制造集成结构的方法，以及形成垂直堆叠的存储单元的方法
公开(公告)号：US09305938B2
公开(公告)日：2016-04-05
申请号：US14824942
申请日：2015-08-12
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Aaron R. Wilson
IPC分类号： H01L27/115 , H01L27/108
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/02238 , H01L21/31144 , H01L21/32139 , H01L27/10844 , H01L27/11524 , H01L27/11556 , H01L27/1157 , H01L29/4966
摘要： Some embodiments include a method of fabricating integrated structures. A metal-containing material is formed over a stack of alternating first and second levels. An opening is formed through the metal-containing material and the stack. Repeating vertically-stacked electrical components are formed along the stack at sidewalls of the opening. Some embodiments include a method of forming vertically-stacked memory cells. Metal-containing material is formed over a stack of alternating silicon dioxide levels and conductively-doped silicon levels. A first opening is formed through the metal-containing material and the stack. Cavities are formed to extend into the conductively-doped silicon levels along sidewalls of the first opening. Charge-blocking dielectric and charge-storage structures are formed within the cavities to leave a second opening. Sidewalls of the second opening are lined with gate dielectric and then channel material is formed within the second opening.
摘要翻译：一些实施例包括制造集成结构的方法。在交替的第一和第二水平的叠层上形成含金属的材料。通过含金属材料和叠层形成开口。在开口的侧壁处沿着堆叠形成重叠的垂直堆叠的电部件。一些实施例包括形成垂直堆叠的存储单元的方法。含金属的材料形成在交替的二氧化硅水平和导电掺杂的硅层上。通过含金属材料和叠层形成第一开口。腔体形成为延伸到沿着第一开口的侧壁的导电掺杂的硅层中。电荷阻挡电介质和电荷存储结构形成在空腔内以留下第二开口。第二开口的侧壁衬有栅极电介质，然后在第二开口内形成通道材料。

32. 发明授权

US09275909B2 Methods of fabricating semiconductor structures 有权
标题翻译：制造半导体结构的方法
公开(公告)号：US09275909B2
公开(公告)日：2016-03-01
申请号：US13964282
申请日：2013-08-12
申请人： Micron Technology, Inc.
发明人： Srikant Jayanti , Fatma Arzum Simsek-Ege , Pavan Kumar Reddy Aella
IPC分类号： H01L21/336 , H01L21/8239 , H01L21/28 , H01L21/311 , H01L29/66 , H01L29/788 , H01L29/792 , H01L27/115
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/0234 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L21/32134 , H01L21/8239 , H01L27/11551 , H01L27/11556 , H01L29/04 , H01L29/16 , H01L29/511 , H01L29/518 , H01L29/66825 , H01L29/7883 , H01L29/7889 , H01L29/7926
摘要： Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.
摘要翻译：半导体结构可以包括交替的电介质材料和控制栅极的堆叠，与控制栅极横向相邻的电荷存储结构，每个电荷存储结构和横向相邻的控制栅之间的电荷块材料，以及延伸穿过堆叠交替氧化物和控制门。堆叠中的每个介电材料具有不同密度和/或不同的去除速率的至少两个部分。还公开了制造这种半导体结构的方法。

33. 发明授权

US09064970B2 Memory including blocking dielectric in etch stop tier 有权
标题翻译：存储器包括蚀刻停止层中的阻挡电介质
公开(公告)号：US09064970B2
公开(公告)日：2015-06-23
申请号：US13864794
申请日：2013-04-17
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , John Hopkins , Srikant Jayanti
IPC分类号： H01L27/115 , H01L29/792 , H01L29/66
CPC分类号： H01L27/11556 , H01L27/11524 , H01L27/11582 , H01L29/66825 , H01L29/66833 , H01L29/7889 , H01L29/7926
摘要： Vertical memories and methods of making the same are discussed generally herein. In one embodiment, a vertical memory can include a vertical pillar extending to a source, an etch stop tier over the source, and a stack of alternating dielectric tiers and conductive tiers over the etch stop tier. The etch stop tier can comprise a blocking dielectric adjacent to the pillar. In another embodiment, the etch stop tier can comprise a blocking dielectric adjacent to the pillar, and a plurality of dielectric films horizontally extending from the blocking dielectric into the etch stop tier.
摘要翻译：垂直记忆及其制备方法一般在此讨论。在一个实施例中，垂直存储器可以包括延伸到源的垂直柱，源极上的蚀刻停止层，以及蚀刻停止层上方的交替介电层和导电层的堆叠。蚀刻停止层可以包括邻近柱的阻挡电介质。在另一个实施例中，蚀刻停止层可以包括邻近柱的阻挡电介质和从阻挡电介质水平延伸到蚀刻停止层中的多个电介质膜。

34. 发明申请

US20150041879A1 SEMICONDUCTOR STRUCTURES AND METHODS OF FABRICATION OF SAME 有权
标题翻译：半导体结构及其制造方法
公开(公告)号：US20150041879A1
公开(公告)日：2015-02-12
申请号：US13964282
申请日：2013-08-12
申请人： Micron Technology, Inc.
发明人： Srikant Jayanti , Fatma Arzum Simsek-Ege , Pavan Kumar Reddy Aella
IPC分类号： H01L29/66 , H01L29/792 , H01L21/28
CPC分类号： H01L27/11582 , H01L21/02164 , H01L21/022 , H01L21/02274 , H01L21/0234 , H01L21/28273 , H01L21/28282 , H01L21/31111 , H01L21/32134 , H01L21/8239 , H01L27/11551 , H01L27/11556 , H01L29/04 , H01L29/16 , H01L29/511 , H01L29/518 , H01L29/66825 , H01L29/7883 , H01L29/7889 , H01L29/7926
摘要： Semiconductor structures may include a stack of alternating dielectric materials and control gates, charge storage structures laterally adjacent to the control gates, a charge block material between each of the charge storage structures and the laterally adjacent control gates, and a pillar extending through the stack of alternating oxide materials and control gates. Each of the dielectric materials in the stack has at least two portions of different densities and/or different rates of removal. Also disclosed are methods of fabricating such semiconductor structures.
摘要翻译：半导体结构可以包括交替的电介质材料和控制栅极的堆叠，与控制栅极横向相邻的电荷存储结构，每个电荷存储结构和横向相邻的控制栅之间的电荷块材料，以及延伸穿过堆叠交替氧化物和控制门。堆叠中的每个介电材料具有不同密度和/或不同的去除速率的至少两个部分。还公开了制造这种半导体结构的方法。

35. 发明申请

US20140203344A1 3D MEMORY 有权
标题翻译： 3D内存
公开(公告)号：US20140203344A1
公开(公告)日：2014-07-24
申请号：US13748747
申请日：2013-01-24
申请人： MICRON TECHNOLOGY, INC.
发明人： John Hopkins , Darwin Franseda Fan , Fatma Arzum Simsek-Ege , James Brighten , Aurelio Giancarlo Mauri , Srikant Jayanti
IPC分类号： H01L29/423 , H01L29/40
CPC分类号： H01L29/7887 , H01L21/28035 , H01L21/28273 , H01L21/28282 , H01L27/11524 , H01L27/11556 , H01L27/11582 , H01L29/401 , H01L29/42324 , H01L29/518 , H01L29/66825 , H01L29/7827 , H01L29/7881 , H01L29/7889
摘要： Three-dimensional memory cells and methods of making and using the memory cells are discussed generally herein. In one or more embodiments, a three-dimensional vertical memory can include a memory stack. Such a memory stack can include memory cells and a dielectric between adjacent memory cells, each memory cell including a control gate and a charge storage structure. The memory cell can further include a barrier material between the charge storage structure and the control gate, the charge storage structure and the barrier material having a substantially equal dimension.
摘要翻译：三维存储器单元以及制造和使用存储器单元的方法一般在此讨论。在一个或多个实施例中，三维垂直存储器可以包括存储器堆栈。这样的存储器堆可以包括存储器单元和相邻存储单元之间的电介质，每个存储单元包括控制栅极和电荷存储结构。存储单元还可以包括电荷存储结构和控制栅极之间的阻挡材料，电荷存储结构和阻挡材料具有基本相等的尺寸。

36. 发明公开

US20240172425A1 MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS 审中-公开
公开(公告)号：US20240172425A1
公开(公告)日：2024-05-23
申请号：US18429004
申请日：2024-01-31
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege
IPC分类号： H10B12/00 , H01L25/065 , H10B80/00
CPC分类号： H10B12/485 , H01L25/0657 , H10B12/0335 , H10B12/315 , H10B12/482 , H10B12/488 , H10B12/50 , H10B80/00
摘要： A method of forming a microelectronic device comprises forming a microelectronic device structure comprising memory cells, digit lines, word lines, and at least one isolation material covering and surrounding the memory cells, the digit lines, and the word lines. An additional microelectronic device structure comprising control logic devices and at least one additional isolation material covering and surrounding the control logic devices is formed. The additional microelectronic device structure is attached to the microelectronic device structure. Contact structures are formed to extend through the at least one isolation material and the at least one additional isolation material. Some of the contact structures are coupled to some of the digit lines and some of the control logic devices. Some other of the contact structures are coupled to some of the word lines and some other of the control logic devices. Microelectronic devices, electronic systems, and additional methods are also described.

37. 发明授权

US11925031B2 Arrays of capacitors and arrays of memory cells 有权
公开(公告)号：US11925031B2
公开(公告)日：2024-03-05
申请号：US17950968
申请日：2022-09-22
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Durai Vishak Nirmal Ramaswamy
IPC分类号： H10B53/30 , H01L21/768 , H01L49/02 , H10B12/00 , H10B53/10
CPC分类号： H10B53/30 , H01L21/7688 , H01L28/60 , H10B12/0335 , H10B53/10
摘要： A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group.

38. 发明授权

US11924730B2 Operating emergency prevention sensor systems 有权
公开(公告)号：US11924730B2
公开(公告)日：2024-03-05
申请号：US17101761
申请日：2020-11-23
申请人： Micron Technology, Inc.
发明人： Shruthi Kumara Vadivel , Anshika Sharma , Deepti Verma , Fatma Arzum Simsek-Ege , Trupti D. Gawai , Lavanya Sriram
IPC分类号： H04W4/90 , B64C39/02 , G01V1/00 , G08B7/06 , H04W4/021 , H04W76/50
CPC分类号： H04W4/90 , B64C39/024 , G01V1/008 , G08B7/066 , H04W4/022 , H04W76/50
摘要： Methods, systems, and devices for operating emergency prevention sensor systems are described. Devices can include a plurality of components including a sensor component, a processor, and memory. In an example, a method can include receiving at a processor signaling from a plurality of environmental sensing devices, each having at least one biodegradable component, in an area of concern, wherein the area of concern corresponds to a particular set of coordinates in a database, determining environmental characteristics of an emergency associated with the area of concern based, at least in part, on the signaling, and determining a preventive action based on the determined characteristics. In another example, a number of components of the sensing devices are biodegradable.

39. 发明公开

US20240071467A1 WORD LINE DRIVERS FOR MULTIPLE-DIE MEMORY DEVICES 审中-公开
公开(公告)号：US20240071467A1
公开(公告)日：2024-02-29
申请号：US17893654
申请日：2022-08-23
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Mingdong Cui
IPC分类号： G11C11/408 , H10B80/00
CPC分类号： G11C11/4085 , G11C11/4087 , H10B80/00
摘要： Methods, systems, and devices for word line drivers for multiple-die memory devices are described. A memory device may include a first semiconductor die associated with at least memory cells and corresponding access lines of the memory device, and a second semiconductor die associated with at least access line driver circuitry of the memory device. The second semiconductor die may be located in contact with or otherwise adjacent to the first semiconductor die, and electrical contacts may be formed to couple the access line driver circuitry of the second semiconductor die with the access line conductors of the first semiconductor die. For example, cavities may be formed through the second semiconductor die and at least a portion of the first semiconductor die, and the electrical contacts may be formed between the semiconductor dies at least in part from forming a conductive material in the cavities.

40. 发明公开

US20240047428A1 MEMORY DEVICES AND ELECTRONIC SYSTEMS 审中-公开
公开(公告)号：US20240047428A1
公开(公告)日：2024-02-08
申请号：US18491678
申请日：2023-10-20
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege
IPC分类号： H01L25/065 , H01L23/528 , H01L23/532 , H01L23/00 , H01L25/00
CPC分类号： H01L25/0657 , H01L23/528 , H01L23/53228 , H01L24/08 , H01L24/80 , H01L25/50 , H01L2224/80896 , H01L2225/06541 , H01L2224/08145
摘要： A microelectronic device comprises a first microelectronic device structure and a second microelectronic device structure attached to the first microelectronic device structure. The first microelectronic device structure comprises a memory array region comprising a stack structure comprising levels of conductive structures vertically alternating with levels of insulative structures, and staircase structures at lateral ends of the stack structure. The memory array region further comprises vertical stacks of memory cells, at least one of the vertical stacks of memory cells comprising stacked capacitor structures, each stacked capacitor structure comprising capacitor structures vertically spaced from each other by at least a level of the levels of insulative structures, transistor structures, each transistor structure operably coupled to a capacitor structure and to one of the conductive structures of the levels of conductive structures, and a conductive pillar structure vertically extending through the transistor structures.

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