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1. 发明申请

US20230069570A1 TREATMENT PLAN IDENTIFICATION 有权
公开(公告)号：US20230069570A1
公开(公告)日：2023-03-02
申请号：US17411801
申请日：2021-08-25
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Deepti Verma , Shruthi Kumara Vadivel
IPC分类号： G16H20/00 , G16H50/30 , G16H50/20
摘要： Methods and non-transitory machine-readable media associated with treatment plan identification are described. Treatment plan identification can include receiving first signaling configured to monitor user health data and receiving second signaling configured to monitor user behavior data. Treatment plan identification can include writing data that is based at least in part on a combination of the first signaling and the second signaling and identifying output data representative of a treatment plan for the user based at least in part on input data representative of the written data and additional user data. Output data representative of the treatment plan can be transmitted to a computing device accessible by the user, a computing device accessible by a provider, or both.

2. 发明申请

US20230043108A1 VERTICAL TRANSISTOR FUSE LATCHES 有权
公开(公告)号：US20230043108A1
公开(公告)日：2023-02-09
申请号：US17396341
申请日：2021-08-06
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Yuan He
IPC分类号： H01L23/525 , H01L27/108
摘要： Methods, systems, and devices for vertical transistor fuse latches are described. An apparatus may include a substrate and a memory array that is coupled with the substrate. The apparatus may also include a latch that is configured to store information from a fuse for the memory array. The latch may be at least partially within an additional substrate separate from and above the substrate. The latch may include a quantity of p-type vertical transistors and a quantity of n-type vertical transistors each at least partially disposed within the additional substrate above the substrate.

3. 发明申请

US20230013333A1 Array of Capacitors, Array of Memory Cells, Methods of Forming an Array of Capacitors, and Methods of Forming an Array of Memory Cells 有权
公开(公告)号：US20230013333A1
公开(公告)日：2023-01-19
申请号：US17950968
申请日：2022-09-22
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Durai Vishak Nirmal Ramaswamy
IPC分类号： H01L27/11507 , H01L27/108 , H01L27/11504 , H01L49/02 , H01L21/768
摘要： A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group

4. 发明申请

US20230005903A1 METHODS OF FORMING MICROELECTRONIC DEVICES, AND RELATED MICROELECTRONIC DEVICES AND ELECTRONIC SYSTEMS 有权
公开(公告)号：US20230005903A1
公开(公告)日：2023-01-05
申请号：US17364476
申请日：2021-06-30
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Kunal R. Parekh
IPC分类号： H01L25/18 , H01L27/108 , H01L25/00 , H01L23/00
摘要： A method of forming a microelectronic device comprises forming a microelectronic device structure assembly comprising memory cells, digit lines coupled to the memory cells, contact structures coupled to the digit lines, word lines coupled to the memory cells, additional contact structures coupled to the word lines, and isolation material surrounding the contact structures and the additional contact structures and overlying the memory cells. An additional microelectronic device structure assembly is formed and comprises control logic devices, further contact structures coupled to the control logic devices, and additional isolation material surrounding the further contact structures and overlying the control logic devices. The additional microelectronic device structure assembly is attached to the microelectronic device structure assembly by bonding the additional isolation material to the isolation material and by bonding the further contact structures to the contact structures and the additional contact structures. Microelectronic devices and electronic systems are also described.

5. 发明申请

US20220399308A1 MICROELECTRONIC DEVICES, RELATED MEMORY DEVICES AND ELECTRONIC SYSTEMS, AND METHODS OF FORMING MICROELECTRONIC DEVICES 有权
公开(公告)号：US20220399308A1
公开(公告)日：2022-12-15
申请号：US17344444
申请日：2021-06-10
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Yuan He
IPC分类号： H01L25/065 , H01L25/18 , H01L25/00
摘要： A microelectronic device comprises a first control logic region comprising first control logic devices and a memory array region vertically overlying the first control logic region. The memory array region comprises capacitors, access devices laterally neighboring and in electrical communication with the capacitors, conductive lines operatively associated with the access devices and extending in a lateral direction, and first conductive pillars operatively associated with the access devices and vertically extending through the memory array region. The microelectronic device further comprises a second control logic region comprising second control logic devices vertically overlying the memory array region. Related microelectronic devices, memory devices, electronic systems, and methods are also described.

6. 发明申请

US20220375930A1 TRANSISTOR CONFIGURATIONS FOR MULTI-DECK MEMORY DEVICES 有权
公开(公告)号：US20220375930A1
公开(公告)日：2022-11-24
申请号：US17326286
申请日：2021-05-20
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege
IPC分类号： H01L27/06 , G11C5/06 , H01L23/538 , H01L27/092 , H01L21/8238 , H01L25/065
摘要： Methods, systems, and devices for transistor configurations for multi-deck memory devices are described. A memory device may include a first set of transistors formed in part by doping portions of a first semiconductor substrate of the memory device. The memory device may include a set of memory cells arranged in a stack of decks of memory cells above the first semiconductor substrate and a second semiconductor substrate bonded above the stack of decks. The memory device may include a second set of transistors formed in part by doping portions of the second semiconductor substrate. The stack of decks may include a lower set of one or more decks that is coupled with the first set of transistors and an upper set of one or more decks that is coupled with the second set of transistors.

7. 发明授权

US11476262B2 Methods of forming an array of capacitors 有权
公开(公告)号：US11476262B2
公开(公告)日：2022-10-18
申请号：US16941174
申请日：2020-07-28
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Durai Vishak Nirmal Ramaswamy
IPC分类号： H01L27/11507 , H01L27/11504 , H01L21/768 , H01L49/02 , H01L27/108
摘要： A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group.

8. 发明申请

US20220131003A1 MEMORY ARRAYS WITH VERTICAL TRANSISTORS AND THE FORMATION THEREOF 有权
公开(公告)号：US20220131003A1
公开(公告)日：2022-04-28
申请号：US17568133
申请日：2022-01-04
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Steve V. Cole , Scott J. Derner , Toby D. Robbs
IPC分类号： H01L29/78 , H01L29/66 , H01L27/108 , H01L27/11587 , G11C11/22 , G11C11/4091
摘要： An apparatus, such as a memory array, can have a memory cell coupled to a first digit line (e.g., a local digit line) at a first level. A second digit line (e.g., hierarchical digit line) at a second level can be coupled to a main sense amplifier. A charge sharing device at a third level between the first and second levels can be coupled to the first digit line and to a connector. A vertical transistor at the third level can be coupled between the first digit line and the connector. A contact can be coupled between the connector and the second digit line.

9. 发明申请

US20220037342A1 Array Of Capacitors, Array Of Memory Cells, Methods Of Forming An Array Of Capacitors, And Methods Of Forming An Array Of Memory Cells 有权
公开(公告)号：US20220037342A1
公开(公告)日：2022-02-03
申请号：US16941174
申请日：2020-07-28
申请人： Micron Technology, Inc.
发明人： Fatma Arzum Simsek-Ege , Durai Vishak Nirmal Ramaswamy
IPC分类号： H01L27/11507 , H01L27/11504 , H01L27/108 , H01L49/02
摘要： A method of forming an array of capacitors comprises forming rows and columns of horizontally-spaced openings in a sacrificial material. Fill material is formed in multiple of the columns of the openings and lower capacitor electrodes a are formed in a plurality of the columns that are between the columns of the openings comprising the fill material therein. The fill material is of different composition from that of the lower capacitor electrodes. The fill material is between a plurality of horizontally-spaced groups that individually comprises the lower capacitor electrodes. Immediately-adjacent of the groups are horizontally spaced apart from one another by a gap that comprises at least one of the columns of the openings comprising the fill material therein. The sacrificial material is removed to expose laterally-outer sides of the lower capacitor electrodes. A capacitor insulator is formed over tops and the laterally-outer sides of the lower capacitor electrodes. Upper capacitor electrode material is formed over the capacitor insulator and the lower capacitor electrodes. A horizontally-elongated conductive line is formed atop individual of the groups that directly electrically couple together the upper capacitor electrode material there-below in that individual group

10. 发明授权

US11171206B2 Channel conduction in semiconductor devices 有权
公开(公告)号：US11171206B2
公开(公告)日：2021-11-09
申请号：US16509093
申请日：2019-07-11
申请人： Micron Technology, Inc.
发明人： Kamal M. Karda , Haitao Liu , Si-Woo Lee , Fatma Arzum Simsek-Ege , Deepak Chandra Pandey , Chandra V. Mouli , John A. Smythe, III
IPC分类号： H01L29/06 , H01L27/108 , H01L21/762
摘要： An example apparatus includes a first source/drain region and a second source/drain region formed in a substrate to form an active area of the apparatus. The first source/drain region and the second source/drain region are separated by a channel. The apparatus includes a gate opposing the channel. A sense line is coupled to the first source/drain region and a storage node is coupled to the second source/drain region. An isolation trench is adjacent to the active area. The trench includes a dielectric material with a conductive bias opposing the conductive bias of the channel in the active area.

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