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31. 发明申请

US20190195700A1 MIDDLE-OF-LINE (MOL) METAL RESISTOR TEMPERATURE SENSORS FOR LOCALIZED TEMPERATURE SENSING OF ACTIVE SEMICONDUCTOR AREAS IN INTEGRATED CIRCUITS (ICs) 审中-公开
公开(公告)号：US20190195700A1
公开(公告)日：2019-06-27
申请号：US16268669
申请日：2019-02-06
申请人： QUALCOMM Incorporated
发明人： Lixin Ge , Periannan Chidambaram , Bin Yang , Jiefeng Jeff Lin , Giridhar Nallapati , Bo Yu , Jie Deng , Jun Yuan , Stanley Seungchul Song
IPC分类号： G01K7/01 , H01L23/522 , H01L23/34 , G01K7/18 , H01L49/02 , G01K7/24 , H01L21/768 , H01L21/3213 , H01L23/528 , H01L21/66
CPC分类号： G01K7/01 , G01K7/186 , G01K7/24 , H01L21/32139 , H01L21/76895 , H01L22/34 , H01L23/34 , H01L23/5228 , H01L23/528 , H01L27/0629 , H01L28/24
摘要： Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

32. 发明授权

US10263080B2 Transistor with fluorinated graphene spacer 有权
公开(公告)号：US10263080B2
公开(公告)日：2019-04-16
申请号：US15672017
申请日：2017-08-08
申请人： QUALCOMM Incorporated
发明人： Ye Lu , Junjing Bao , Bin Yang , Lixin Ge , Yun Yue
IPC分类号： H01L29/66 , H01L29/16 , H01L21/02 , H01L29/10 , H01L29/72 , H01L29/78
摘要： An integrated circuit (IC) device may include a semiconductor structure. The semiconductor structure may include a source contact, a drain contact, and a gate. A first fluorocarbon spacer may be between the gate and the source contact. A second fluorocarbon spacer may be between the gate and the drain contact.

33. 发明申请

US20190088660A1 BI-STABLE STATIC RANDOM ACCESS MEMORY (SRAM) BIT CELLS THAT FACILITATE DIRECT WRITING FOR STORAGE 审中-公开
公开(公告)号：US20190088660A1
公开(公告)日：2019-03-21
申请号：US15708913
申请日：2017-09-19
申请人： QUALCOMM Incorporated
发明人： Xia Li , Seung Hyuk Kang , Bin Yang , Gengming Tao
IPC分类号： H01L27/11 , H01L29/10 , H01L29/08 , H01L29/06 , H01L29/423 , H01L29/417 , H01L29/165 , H01L29/16 , H01L21/762 , H01L21/027 , H01L21/306 , H01L21/3105 , G11C11/419
摘要： Bi-stable static random access memory (SRAM) bit cells that facilitate direct writing for storage are disclosed. In one aspect, a bi-stable SRAM bit cell includes source and drain regions, and a gate region formed over a well region between the source and drain regions, which results in two (2) bipolar junction transistors (BJTs) formed within a bi-stable SRAM bit cell. A base tap region and a collector tap region are employed to provide voltages for read and write operations. The base tap region is formed beside a shallow trench isolation (STI) region having a bottom surface higher in a Y-axis direction in the well region than a bottom surface of the well region. The collector tap region is formed on one side of an STI region having a bottom surface lower in the Y-axis direction in the substrate than the bottom surface of the well region.

34. 发明授权

US10205018B1 Planar double gate semiconductor device 有权
公开(公告)号：US10205018B1
公开(公告)日：2019-02-12
申请号：US15676494
申请日：2017-08-14
申请人： QUALCOMM Incorporated
发明人： Xia Li , Bin Yang , Gengming Tao
IPC分类号： H01L29/78 , H01L29/66 , H01L29/16 , H01L27/092 , H01L21/8238
摘要： Certain aspects of the present disclosure generally relate to a semiconductor device. The semiconductor device generally includes a substrate, a channel disposed above the substrate, and a first dielectric layer disposed adjacent to a first side of the channel. The semiconductor device may also include a first non-insulative region disposed between the first dielectric layer and the substrate, and a second dielectric layer disposed adjacent to a second side of the channel, wherein the first dielectric layer and the second dielectric layer comprise high-k layers. In certain aspects, a second non-insulative region may be disposed above the second dielectric layer, and a third non-insulative region may be disposed adjacent to a third side of the channel.

35. 发明授权

US10084074B1 Compound semiconductor field effect transistor gate length scaling 有权
公开(公告)号：US10084074B1
公开(公告)日：2018-09-25
申请号：US15643815
申请日：2017-07-07
申请人： QUALCOMM Incorporated
发明人： Bin Yang , Gengming Tao , Xia Li , Periannan Chidambaram
IPC分类号： H01L29/423 , H01L29/778 , H01L29/66
摘要： A compound semiconductor transistor may include a channel layer. The compound semiconductor transistor may also include a dielectric layer on the channel layer. The compound semiconductor transistor may further include a gate. The gate may include a vertical base portion through the dielectric layer and electrically contacting the channel layer. The gate may also include a head portion on the dielectric layer and electrically coupled to the vertical base portion of the gate.

36. 发明授权

US10026731B1 Compound semiconductor transistor integration with high density capacitor 有权
公开(公告)号：US10026731B1
公开(公告)日：2018-07-17
申请号：US15488108
申请日：2017-04-14
申请人： QUALCOMM Incorporated
发明人： Bin Yang , Xia Li , Gengming Tao
IPC分类号： H01L29/20 , H01L27/06 , H01L49/02 , H01L29/737
摘要： A metal-insulator-metal (MIM) capacitor includes a compound semiconductor substrate. The MIM capacitor includes a collector contact layer on the compound semiconductor substrate, a first dielectric layer on the collector contact layer, a conductive electrode layer on the first dielectric layer, and a second dielectric layer on the conductive electrode layer. The MIM capacitor includes a first conductive interconnect on the second dielectric layer, a third dielectric layer on the first conductive interconnect, and a second conductive interconnect on the third dielectric layer. A first capacitive component includes the collector contact layer, the conductive electrode layer, and the first dielectric layer. A second capacitive component includes the first conductive interconnect, the conductive electrode layer and the second dielectric layer. A third capacitive component includes the second conductive interconnect, the first conductive interconnect, and the third dielectric layer. The first, second, and third capacitive components are arranged in parallel with each other.

37. 发明申请

US20180058943A1 MIDDLE-OF-LINE (MOL) METAL RESISTOR TEMPERATURE SENSORS FOR LOCALIZED TEMPERATURE SENSING OF ACTIVE SEMICONDUCTOR AREAS IN INTEGRATED CIRCUITS (ICs) 审中-公开
公开(公告)号：US20180058943A1
公开(公告)日：2018-03-01
申请号：US15246006
申请日：2016-08-24
申请人： QUALCOMM Incorporated
发明人： Lixin Ge , Chidi Chidambaram , Bin Yang , Jiefeng Jeff Lin , Giridhar Nallapati , Bo Yu , Jie Deng , Jun Yuan , Stanley Seungchul Song
IPC分类号： G01K7/01 , H01L21/66 , H01L49/02 , H01L23/528 , H01L21/3213 , H01L21/768 , G01K7/24
CPC分类号： G01K7/01 , G01K7/186 , G01K7/24 , H01L21/32139 , H01L21/76895 , H01L22/34 , H01L23/34 , H01L23/5228 , H01L23/528 , H01L27/0629 , H01L28/24
摘要： Middle-of-line (MOL) metal resistor temperature sensors for localized temperature sensing of active semiconductor areas in integrated circuits (ICs) are disclosed. One or more metal resistors are fabricated in a MOL layer in the IC adjacent to an active semiconductor area to sense ambient temperature in the adjacent active semiconductor area. Voltage of the metal resistor will change as a function of ambient temperature of the metal resistor, which can be sensed to measure the ambient temperature around devices in the active semiconductor layer adjacent to the metal resistor. By fabricating a metal resistor in the MOL layer, the metal resistor can be localized adjacent and close to semiconductor devices to more accurately sense ambient temperature of the semiconductor devices. The same fabrication processes used to create contacts in the MOL layer can be used to fabricate the metal resistor.

38. 发明授权

US09412818B2 System and method of manufacturing a fin field-effect transistor having multiple fin heights 有权
标题翻译：制造具有多个翅片高度的鳍状场效应晶体管的系统和方法
公开(公告)号：US09412818B2
公开(公告)日：2016-08-09
申请号：US14100489
申请日：2013-12-09
申请人： QUALCOMM Incorporated
发明人： Bin Yang , Xia Li , PR Chidambaram , Choh Fei Yeap
IPC分类号： H01L27/088 , H01L29/06 , H01L29/78 , H01L29/66 , H01L29/20 , H01L29/22 , H01L21/8234
CPC分类号： H01L29/0684 , H01L21/823431 , H01L27/0886 , H01L29/0657 , H01L29/20 , H01L29/22 , H01L29/66795 , H01L29/785
摘要： An apparatus comprises a first fin field effect transistor (FinFET) device extending from a surface of a first etch stop layer. The apparatus also comprises a second FinFET device extending from a surface of a second etch stop layer. A first compound layer is interposed between the first etch stop layer and the second etch stop layer.
摘要翻译：一种装置包括从第一蚀刻停止层的表面延伸的第一鳍状场效应晶体管（FinFET）器件。该装置还包括从第二蚀刻停止层的表面延伸的第二FinFET器件。第一化合物层介于第一蚀刻停止层和第二蚀刻停止层之间。

39. 发明授权

US09373412B2 System and method of programming a memory cell 有权
标题翻译：编程存储器单元的系统和方法
公开(公告)号：US09373412B2
公开(公告)日：2016-06-21
申请号：US14570577
申请日：2014-12-15
申请人： QUALCOMM Incorporated
发明人： Xia Li , Bin Yang
IPC分类号： G11C5/14 , G11C16/30 , G11C16/04 , G11C5/06 , G11C17/18 , G11C7/12 , G06F17/50 , G11C11/40 , G11C17/16 , G11C11/404
CPC分类号： G11C17/18 , G06F17/5045 , G11C5/06 , G11C5/146 , G11C7/12 , G11C11/40 , G11C11/404 , G11C11/5692 , G11C16/04 , G11C17/16 , G11C2211/4016
摘要： An apparatus includes a semiconductor transistor structure. The semiconductor transistor structure includes dielectric material, a channel region, a gate, a source overlap region, and a drain overlap region. The source overlap region is biasable to cause a first voltage difference between the source overlap region and the gate to exceed a breakdown voltage of the dielectric material. The drain overlap region is biasable to cause a second voltage difference between the drain overlap region and the gate to exceed the breakdown voltage. The apparatus includes a well line coupled to a body of the semiconductor transistor. The apparatus includes circuitry configured to apply a voltage to the well line to prevent a breakdown condition between the channel region and the gate.
摘要翻译：一种装置包括半导体晶体管结构。半导体晶体管结构包括电介质材料，沟道区，栅极，源极重叠区域和漏极重叠区域。源重叠区域是可偏置的，以使源重叠区域和栅极之间的第一电压差超过电介质材料的击穿电压。漏极重叠区域是可偏置的，以使漏极重叠区域和栅极之间的第二电压差超过击穿电压。该装置包括耦合到半导体晶体管的本体的阱线。该装置包括被配置为向阱管线施加电压以防止沟道区域和栅极之间的击穿状态的电路。

40. 发明授权

US09252104B2 Complementary back end of line (BEOL) capacitor 有权
标题翻译：互补后端（BEOL）电容
公开(公告)号：US09252104B2
公开(公告)日：2016-02-02
申请号：US14512191
申请日：2014-10-10
申请人： QUALCOMM INCORPORATED
发明人： John J. Zhu , Bin Yang , Pr Chidambaram , Lixin Ge , Jihong Choi
IPC分类号： H01L29/00 , H01L23/538 , H01L27/08 , H01L49/02 , H01L23/522
CPC分类号： H01L23/538 , H01L23/5223 , H01L27/0805 , H01L28/40 , H01L2924/0002 , H01L2924/00
摘要： A complementary back end of line (BEOL) capacitor (CBC) structure includes a metal oxide metal (MOM) capacitor structure. The MOM capacitor structure is coupled to a first upper interconnect layer of an interconnect stack of an integrated circuit (IC) device. The MOM capacitor structure includes a lower interconnect layer of the interconnect stack. The CBC structure also includes a second upper interconnect layer of the interconnect stack coupled to the MOM capacitor structure. The CBC structure also includes a metal insulator metal (MIM) capacitor layer between the first upper interconnect layer and the second upper interconnect layer. In addition, CBC structure also includes a MIM capacitor structure coupled to the MOM capacitor structure. The MIM capacitor structure includes a first capacitor plate having a portion of the first upper interconnect layer, and a second capacitor plate having a portion of the MIM capacitor layer(s).
摘要翻译：互补的后端（BEOL）电容器（CBC）结构包括金属氧化物金属（MOM）电容器结构。 MOM电容器结构耦合到集成电路（IC）器件的互连堆叠的第一上互连层。 MOM电容器结构包括互连叠层的下互连层。 CBC结构还包括耦合到MOM电容器结构的互连叠层的第二上互连层。 CBC结构还包括在第一上部互连层和第二上部互连层之间的金属绝缘体金属（MIM）电容器层。此外，CBC结构还包括耦合到MOM电容器结构的MIM电容器结构。 MIM电容器结构包括具有第一上部互连层的一部分的第一电容器板和具有MIM电容器层的一部分的第二电容器板。

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