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31. 发明授权

US5680362A Circuit and method for accessing memory cells of a memory device 失效
标题翻译：用于访问存储器件的存储器单元的电路和方法
公开(公告)号：US5680362A
公开(公告)日：1997-10-21
申请号：US657637
申请日：1996-05-30
申请人： Michael C. Parris , Douglas B. Butler , Kim C. Hardee
发明人： Michael C. Parris , Douglas B. Butler , Kim C. Hardee
IPC分类号： G11C11/413 , G11C8/12 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/46 , G11C8/00 , G11C7/00
CPC分类号： G11C29/46 , G11C29/34 , G11C8/12
摘要： A circuit and method for concurrently addressing at least two rows of memory cells of a memory array of a memory device. By concurrently addressing at least two rows of memory cells during testing of the memory device during a burn-in period, the memory device can be tested in a reduced time period.
摘要翻译：一种用于同时寻址存储器件的存储器阵列的至少两行存储器单元的电路和方法。通过在老化期间在存储器件测试期间同时寻址至少两行存储器单元，可以在缩短的时间周期内对存储器件进行测试。

32. 发明授权

US5644542A Stress test for memory arrays in integrated circuits 失效
标题翻译：集成电路中存储器阵列的压力测试
公开(公告)号：US5644542A
公开(公告)日：1997-07-01
申请号：US460409
申请日：1995-06-02
申请人： David Charles McClure , James Brady
发明人： David Charles McClure , James Brady
IPC分类号： G01R31/28 , G11C11/413 , G11C29/00 , G11C29/06 , G11C29/34 , G11C29/50 , G11C7/00
CPC分类号： G11C29/34 , G11C29/50 , G11C11/41
摘要： A method for stress testing a memory array in an integrated circuit. Control circuitry selects a plurality of row lines at one time. An overvoltage suitable for stressing the cells of the array is placed on the bit lines. Because a block of cells has been selected, the overvoltage is applied to all cells of the block. The block of cells selected may be either the entire memory array or a portion of the memory array. The selected rows remain selected for the duration of the stress test. Because the overvoltage is applied directly to selected cells, the full overvoltage will be used to stress the transistor gates for the entire test period. In this manner, latent defects within the memory array can be detected.
摘要翻译：一种用于对集成电路中的存储器阵列进行应力测试的方法。控制电路一次选择多行行。适用于对阵列的单元进行加压的过电压放置在位线上。因为已经选择了一个单元块，所以过电压被施加到该块的所有单元。所选择的单元块可以是整个存储器阵列或存储器阵列的一部分。所选行在压力测试期间保持选择。因为过电压直接应用于所选择的单元，所以在整个测试周期中，将使用全过电压来施加晶体管栅极。以这种方式，可以检测存储器阵列内的潜在缺陷。

33. 发明授权

US5644250A Structure for externally identifying an internal state of a semiconductor device 失效
标题翻译：用于外部识别半导体器件的内部状态的结构
公开(公告)号：US5644250A
公开(公告)日：1997-07-01
申请号：US463255
申请日：1995-06-05
申请人： Tsukasa Ooishi
发明人： Tsukasa Ooishi
IPC分类号： G01R31/28 , G01R31/30 , G01R31/3185 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/04 , G11C29/06 , H01L21/66 , H01L21/822 , H01L27/04 , H03K19/00
CPC分类号： G01R31/318505 , G01R31/30
摘要： A semiconductor device includes an inner circuit for executing a predetermined function and setting an internal state thereof in response to an internal state setting signal and a current path forming circuit for forming an additional current path between specific two pads in response to the internal state setting signal. Whether or not the internal state of the semiconductor device has been set to a predetermined state, can be externally identified by detecting a current that flows between these specific two pads. The semiconductor device is provided which can be externally identified in simple structure on whether or not the internal state of the semiconductor device has been set to the predetermined state.
摘要翻译：半导体器件包括用于响应于内部状态设置信号执行预定功能并设置其内部状态的内部电路和用于响应于内部状态设置信号在特定两个焊盘之间形成附加电流路径的电流路径形成电路。半导体器件的内部状态是否被设定为预定状态，可以通过检测在这些特定的两个焊盘之间流动的电流来进行外部识别。提供半导体器件，其可以以简单的结构外部识别半导体器件的内部状态是否已经被设置为预定状态。

34. 发明授权

US5602792A Semiconductor device having supply voltage converting circuits 失效
标题翻译：具有电源电压转换电路的半导体装置
公开(公告)号：US5602792A
公开(公告)日：1997-02-11
申请号：US678146
申请日：1991-04-01
申请人： Yoshikazu Kanaishi
发明人： Yoshikazu Kanaishi
IPC分类号： G11C11/413 , G05F1/46 , G11C5/14 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , H01L21/822 , H01L27/04 , G11C7/00
CPC分类号： G11C5/147 , G05F1/465
摘要： A semiconductor device of the present invention includes an internal circuit within the voltage is pulled down, and two voltage converting circuits for pulling down the external supply voltage. One of the voltage converting circuits supplies a pulled-down voltage to the internal circuit during the normal operation, while the other of the voltage converting circuits operates under a signal from a control circuit, which monitors the voltage level at an external terminal, so as to supply the voltage pulled down from the voltage at the external terminal to the internal circuit. A reliability test, such as burn-in, may be conducted by simply supplying a higher voltage to the external terminal.
摘要翻译：本发明的半导体器件包括电压内部的内部电路被拉下来，以及两个用于拉低外部电源电压的电压转换电路。一个电压转换电路在正常操作期间向内部电路提供下拉电压，而另一个电压转换电路在来自控制电路的信号下工作，该控制电路监视外部端子处的电压电平，以便以将从外部端子的电压下拉的电压提供给内部电路。可以通过简单地向外部端子提供更高的电压来进行可靠性测试，例如老化。

35. 发明授权

US5532618A Stress mode circuit for an integrated circuit with on-chip voltage down converter 失效
标题翻译：具有片上降压转换器的集成电路的应力模式电路
公开(公告)号：US5532618A
公开(公告)日：1996-07-02
申请号：US983328
申请日：1992-11-30
申请人： Kim C. Hardee , Michael V. Cordoba
发明人： Kim C. Hardee , Michael V. Cordoba
IPC分类号： G01R31/26 , G01R31/28 , G05F1/46 , G11C11/401 , G11C11/407 , G11C11/413 , G11C29/00 , G11C29/06 , H03K17/00
CPC分类号： G05F1/465
摘要： A stress mode circuit is provided to generate a voltage that is either equal to a reference voltage or is a proportion of an external voltage (VCCEXT). The circuit includes two voltage divider circuits to provide the proportion voltage. Two differential amplifiers are provided to generate outputs corresponding to a comparison to the proportion voltage and the reference voltage. The outputs operate switches that couple the reference voltage or the proportion voltage to an output terminal.
摘要翻译：提供应力模式电路以产生等于参考电压的电压或者是外部电压（VCCEXT）的比例。该电路包括两个分压电路，以提供比例电压。提供两个差分放大器以产生对应于比例电压和参考电压的比较的输出。输出操作将参考电压或比例电压耦合到输出端子的开关。

36. 发明授权

US5471429A Burn-in circuit and method therefor of semiconductor memory device 失效
标题翻译：老化电路及其半导体存储器件的方法
公开(公告)号：US5471429A
公开(公告)日：1995-11-28
申请号：US348180
申请日：1994-11-28
申请人： Seung-Keun Lee , Choong-Keun Kwak
发明人： Seung-Keun Lee , Choong-Keun Kwak
IPC分类号： G01R31/26 , G01R31/28 , G11C29/00 , G11C29/06 , G11C29/34 , H01L21/66 , G11C7/00
CPC分类号： G11C29/34 , G01R31/2856
摘要： The present invention pertains to semiconductor memory devices and more particularly to a burn-in circuit of such devices and burn-in method which improve reliability of a static random access memory RAM. The semiconductor memory device according to the present invention, which includes a memory cell array in which a plurality of memory cells are stored in the directions of row and column, a row decoder for selecting the row of the memory cell array, and a column decoder for selecting the column of the memory cell array, comprises an input/output line control circuit formed between a data input/output pin disposed on the same chip and the column of the memory cell array for transmitting data inputted/outputted through the data input/output pin, a read/write control circuit for supplying a signal which controls input/output of data in the memory cell array to the input/output line control circuit, and a burn-in control circuit for inputting the output signal of the read/write control circuit, supplying a burn-in signal responsive to the data input through the input/output line control circuit to the row decoder and column decoder, and enabling a burn-in test of the same chip after a package process.
摘要翻译：本发明涉及半导体存储器件，更具体地说，涉及提高静态随机存取存储器RAM的可靠性的这种器件的老化电路和老化方法。根据本发明的半导体存储器件，其包括存储单元阵列，其中多个存储器单元被存储在行和列的方向上，行解码器用于选择存储单元阵列的行，以及列解码器用于选择存储单元阵列的列，包括形成在设置在同一芯片上的数据输入/输出引脚和存储单元阵列的列之间的输入/输出线控制电路，用于发送通过数据输入/ 输出引脚，用于将控制存储单元阵列中的数据的输入/输出的信号提供给输入/输出线控制电路的读/写控制电路，以及用于输入读/写控制电路的输出信号的老化控制电路，写入控制电路，响应于通过输入/输出线路控制电路输入的数据向行解码器和列解码器提供老化信号，以及在一个包之后启用相同芯片的老化测试年龄过程。

37. 发明授权

US5467356A Burn-in circuit and burn-in test method 失效
标题翻译：老化电路和老化测试方法
公开(公告)号：US5467356A
公开(公告)日：1995-11-14
申请号：US101243
申请日：1993-08-02
申请人： Yun-Ho Choi
发明人： Yun-Ho Choi
IPC分类号： G06F11/22 , G11C11/401 , G11C11/407 , G11C29/00 , G11C29/06 , G11C29/50 , G11C29/56
CPC分类号： G11C29/50 , G11C11/401
摘要： A burn-in enable circuit and burn-in test method of a semiconductor memory device are disclosed. A high voltage exceeding the external power voltage by a predetermined amount is applied to at least one of a plurality of pins normally used with a connected semiconductor memory chip to initiate a burn-in test mode. The burn-in test enable circuit senses this high voltage and causes the reset operation of word lines in the chip to become disabled. This allows for a high stress voltage to be applied to all access transistors in the chip simultaneously during a burn-in test for substantially the same amount of time. Therefore, burn-in time is substantially reduced and a reliable burn-in test is obtained.
摘要翻译：公开了一种半导体存储器件的老化实现电路和老化测试方法。将超过外部电源电压的高电压施加到通常与连接的半导体存储器芯片一起使用的多个引脚中的至少一个以启动老化测试模式。老化测试使能电路感测到这个高电压，并导致芯片中字线的复位操作变为禁止。这允许在老化测试期间同时施加高应力电压到芯片中的所有存取晶体管，同时大致相同的时间量。因此，大大降低了老化时间并获得可靠的老化测试。

38. 发明授权

US5452253A Burn-in test circuit for semiconductor memory device 失效
标题翻译：半导体存储器件的老化测试电路
公开(公告)号：US5452253A
公开(公告)日：1995-09-19
申请号：US125574
申请日：1993-09-23
申请人： Young-Keun Choi
发明人： Young-Keun Choi
IPC分类号： G01R31/26 , G01R31/28 , G11C11/401 , G11C29/00 , G11C29/06 , G11C29/14 , G11C29/46 , G11C29/50
CPC分类号： G11C29/46 , G11C29/50
摘要： For enabling burn-in test in a memory device such that a test mode timing signal and detected voltage level of an external power supply are combined in order to maintain compatibility with conventional timing signals, and for preventing the burn-in test circuit from dissipating power in a standby state, there is provided a sense control circuit for producing a short duration enable pulse in response to an input level of timing signals such as WCBR, CBR, or ROR, and a voltage sensor for sensing the input voltage level of the external power supply voltage during the short duration pulse. Also, the circuit includes a burn-in sensor which generates a signal output which determines set or reset of the burn-in test mode in response to the timing signals and the detected level of the voltage sensor. Since the voltage sensor is operated only when the short duration pulse is applied, the power consumption in the voltage sensor is negligible even during the sensing operation of the external supply voltage. Further, the burn-in test mode is activated in the memory device if the external input signals satisfy the particular condition and the level of the external supply voltage is higher than the preset burn-in test voltage, thereby the memory device is prevented from entering into the burn-in test mode due to noise of the external power supply voltage.
摘要翻译：为了在存储器件中实现老化测试，使得测试模式定时信号和外部电源的检测电压电平相结合，以便保持与常规定时信号的兼容性，并且防止老化测试电路消耗功率在待机状态下，提供了用于响应于诸如WCBR，CBR或ROR的定时信号的输入电平产生短持续时间使能脉冲的感测控制电路，以及用于感测外部的输入电压电平的电压传感器在短脉冲期间的电源电压。此外，电路包括老化传感器，其产生响应于定时信号和检测到的电压传感器的电平而确定老化测试模式的设置或复位的信号输出。由于电压传感器仅在施加短持续脉冲时才起作用，因此即使在外部电源电压的感测操作期间，电压传感器的功耗也可忽略不计。此外，如果外部输入信号满足特定条件并且外部电源电压的电平高于预设的老化测试电压，则在存储器件中激活老化测试模式，从而防止存储器件进入由于外部电源电压的噪声，进入老化测试模式。

39. 发明授权

US5428576A Semiconductor device and method of screening the same 失效
标题翻译：半导体器件及其筛选方法
公开(公告)号：US5428576A
公开(公告)日：1995-06-27
申请号：US325636
申请日：1994-10-19
申请人： Tohru Furuyama
发明人： Tohru Furuyama
IPC分类号： G11C11/407 , G11C5/14 , G11C11/401 , G11C11/408 , G11C11/409 , G11C29/00 , G11C29/06 , G11C29/46 , G11C29/50 , G11C7/00 , G11C8/00
CPC分类号： G11C11/4085 , G11C29/46 , G11C29/50 , G11C5/145 , G11C5/147 , G11C11/401
摘要： A semiconductor device comprising a plurality of circuit blocks to which various potentials, including at least one potential either raised or lowered, are assigned. The device further comprises means for selectively and reversely changing the potentials assigned to the circuit blocks.
摘要翻译：一种包括多个电路块的半导体器件，其中分配了包括至少一个升高或降低的电位的各种电位。该装置还包括用于选择性地和反向地改变分配给电路块的电位的装置。

40. 发明授权

US5424990A Semiconductor memory having built-in voltage stress test mode 失效
标题翻译：具有内置电压应力测试模式的半导体存储器
公开(公告)号：US5424990A
公开(公告)日：1995-06-13
申请号：US175537
申请日：1993-12-30
申请人： Takashi Ohsawa
发明人： Takashi Ohsawa
IPC分类号： G11C29/00 , G01R31/28 , G11C11/401 , G11C11/407 , G11C29/06 , G11C29/34 , G11C29/50 , G11C7/00
CPC分类号： G11C29/34 , G11C29/50 , G11C11/401
摘要： There is provided a semiconductor memory with which the duty ratio of column selection lines can be raised as well as that of word lines so that the word lines and the column selection lines of the semiconductor memory may be subjected to a screening test along with the peripheral circuits under a same condition for all these components (in terms of electric field and time) while operating the peripheral circuits. The semiconductor memory comprises a memory circuit including a memory cell array and its peripheral circuits, a first circuit for selecting some of the word lines of the memory cell array, the first means being so adapted to select a greater number of word lines for a voltage stress test mode than for a normal operation mode and a second circuit for selecting some of the column selection lines CSL to thereby select the corresponding columns of the memory cell array, the second means being so adapted to select a greater number of column selection lines for a voltage stress test mode than for a normal operation mode.
摘要翻译：提供了可以提高列选择线的占空比以及字线的占空比的半导体存储器，使得半导体存储器的字线和列选择线可以与外围设备一起进行筛选测试在操作外围电路时，所有这些组件（在电场和时间方面）处于相同条件下的电路。半导体存储器包括存储器电路，其包括存储单元阵列及其周边电路，用于选择存储单元阵列的一些字线的第一电路，第一装置适于选择更多数量的字线用于电压压力测试模式和用于选择一些列选择线CSL的第二电路，从而选择存储单元阵列的相应列，第二装置适于选择更多数量的列选择线，以供电压应力测试模式比正常操作模式。

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