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1. 发明授权

US10891185B2 Error counters on a memory device 有权
公开(公告)号：US10891185B2
公开(公告)日：2021-01-12
申请号：US15314831
申请日：2014-08-08
申请人： HEWLETT PACKARD ENTERPRISE DEVELOPMENT LP
发明人： Lidia Warnes , Melvin K. Benedict , Andrew C. Walton
IPC分类号： G11C29/06 , G06F11/10 , G11C29/44 , G11C29/50 , G11C29/12 , G06F5/06 , G06F11/07 , G11C11/41
摘要： Example implementations relate to tracking memory unit errors on a memory device. In example implementations, a memory device may include on-die error-correcting code (ECC) and a plurality of error counters. One of the plurality of error counters may count errors, detected by the on-die ECC, in a memory unit on the memory device. A post package repair (PPR) may be initiated on the memory device in response to a determination that a value of the one of the plurality of error counters equals a threshold value.

2. 发明授权

US10446222B2 Memory subsystem I/O performance based on in-system empirical testing 有权
公开(公告)号：US10446222B2
公开(公告)日：2019-10-15
申请号：US15372031
申请日：2016-12-07
申请人： Intel Corporation
发明人： Theodore Z. Schoenborn , Christopher P. Mozak
IPC分类号： G06F13/40 , G11C11/4093 , G11C29/56 , G11C29/06 , G11C11/4074 , G11C11/4076 , G11C11/4096 , G11C29/04
摘要： A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.

3. 发明授权

US09830998B2 Stress patterns to detect shorts in three dimensional non-volatile memory 有权
公开(公告)号：US09830998B2
公开(公告)日：2017-11-28
申请号：US14716794
申请日：2015-05-19
申请人： SANDISK TECHNOLOGIES INC.
发明人： Jayavel Pachamuthu , Sagar Magia , Ankitkumar Babariya , Jagdish Sabde
IPC分类号： G11C29/10 , G11C29/06 , G11C29/02 , G11C5/02 , G11C16/34 , G11C29/50 , G11C16/04 , H01L27/11582
CPC分类号： G11C29/025 , G11C5/025 , G11C16/0483 , G11C16/349 , G11C16/3495 , G11C29/06 , G11C29/10 , G11C29/50008 , H01L27/11582
摘要： A non-volatile storage system includes a three dimensional structure comprising vertical columns of memory cells and a managing circuit in communication with the vertical columns. The managing circuit applies one or more patterns of stress voltages to the vertical columns, with different voltages applied to each vertical column of pairs of adjacent vertical columns being tested for shorts. The managing circuit tests for a short in the pairs of adjacent vertical columns after applying the one or more patterns of stress voltages. In one embodiment, the test may comprise programming a memory cell in each vertical column with data that matches the pattern of stress voltages, reading from the memory cells and determining whether data read matches data programmed. The applying of the stress voltages and the testing can be performed as part of a test during manufacturing or in the field during user operation.

4. 发明授权

US09570199B2 Traffic and temperature based memory testing 有权
标题翻译：基于流量和温度的内存测试
公开(公告)号：US09570199B2
公开(公告)日：2017-02-14
申请号：US14584372
申请日：2014-12-29
申请人： International Business Machines Corporation
发明人： Diyanesh B. Chinnakkonda Vidyapoornachary , Timothy J. Dell , Joab D. Henderson , Anil B. Lingambudi , Michael D. Pardeik
IPC分类号： G11C29/50 , G11C29/06 , G11C5/04 , G11C7/04
CPC分类号： G11C29/50 , G11C5/04 , G11C7/04 , G11C29/06 , G11C29/50004 , G11C2029/5002
摘要： The method may include accessing, with a first stress test, a plurality of memory modules, the plurality of memory modules coupled in a computer system, the plurality of memory modules including a first module having a first memory characteristic and a second module having a second memory characteristic. The method may include determining for the first module, a first traffic-to-temperature parameter, and determining that the first module was sufficiently stressed in response to determining that the first traffic-to-temperature parameter is within a first traffic-to-temperature range. The method may also include determining, for the second module, a second traffic-to-temperature parameter, and determining that the second module was sufficiently stressed in response to determining that the second traffic-to-temperature parameter is within a second traffic-to-temperature range.
摘要翻译：该方法可以包括通过第一压力测试访问多个存储器模块，所述多个存储器模块耦合在计算机系统中，所述多个存储器模块包括具有第一存储器特性的第一模块和具有第二存储器特性的第二模块记忆特征。该方法可以包括为第一模块确定第一业务对温度参数，并且响应于确定第一业务对温度参数在第一业务对温度内，确定第一模块被充分应力范围。该方法还可以包括为第二模块确定第二业务对温度参数，并且响应于确定第二业务对温度参数在第二业务到第 -温度范围。

5. 发明授权

US09564216B2 Stress trim and modified ISPP procedures for PCM 有权
标题翻译： PCM的应力修剪和修改的ISPP程序
公开(公告)号：US09564216B2
公开(公告)日：2017-02-07
申请号：US14682903
申请日：2015-04-09
申请人： MACRONIX INTERNATIONAL CO., LTD.
发明人： Win-San Khwa , Tzu-Hsiang Su , Chao-I Wu , Hsiang-Pang Li
IPC分类号： G11C11/00 , G11C13/00 , G11C11/56 , G11C29/02 , G11C29/06 , G11C29/50 , G11C29/04
CPC分类号： G11C13/0069 , G11C11/5678 , G11C13/0004 , G11C13/0023 , G11C13/0064 , G11C29/028 , G11C29/06 , G11C29/50 , G11C29/50008 , G11C2013/0066 , G11C2013/0083 , G11C2029/0409
摘要： A memory circuit is described that includes an array of memory cells including a plurality of blocks. The circuit includes a controller including logic to execute program sequences for selected blocks in the plurality of blocks. The program sequences include patterns of program/verify cycles. The circuit includes logic to assign different patterns of program/verify cycles to different blocks in the plurality of blocks. The circuit includes logic to change a particular pattern assigned to a particular block in the plurality of blocks. The circuit includes logic to maintain statistics for blocks in the plurality of blocks, about performance of cells in the blocks in response to the patterns of program/verify cycles assigned to the blocks. The controller includes logic to apply a stress sequence to one of the selected blocks, the stress sequence including stress pulses applied to memory cells in the one of the selected blocks.
摘要翻译：描述了包括包括多个块的存储器单元的阵列的存储器电路。该电路包括控制器，该控制器包括用于对多个块中的选定块执行程序序列的逻辑。程序序列包括程序/验证周期的模式。该电路包括用于将不同模式的程序/验证周期分配给多个块中的不同块的逻辑。电路包括用于改变分配给多个块中的特定块的特定模式的逻辑。该电路包括用于维护多个块中的块的统计信息的逻辑，关于分配给块的编程/验证周期的模式的块中的小区的性能。控制器包括将应力序列应用于所选择的块之一的逻辑，应力序列包括施加到所选块中的一个存储单元的应力脉冲。

6. 发明授权

US09536626B2 Memory subsystem I/O performance based on in-system empirical testing 有权
标题翻译：基于系统内部测试的内存子系统I / O性能
公开(公告)号：US09536626B2
公开(公告)日：2017-01-03
申请号：US13763511
申请日：2013-02-08
申请人： Theodore Z. Schoenborn , Christopher P. Mozak
发明人： Theodore Z. Schoenborn , Christopher P. Mozak
IPC分类号： G11C29/06 , G11C29/56 , G11C29/04
CPC分类号： G11C11/4093 , G11C11/4074 , G11C11/4076 , G11C11/4096 , G11C29/06 , G11C29/56 , G11C2029/0401
摘要： A memory subsystem empirically tests performance parameters of I/O with a memory device. Based on the empirical testing, the memory subsystem can set the performance parameters specific to the system in which the memory subsystem is included. A test system performs the testing. For each of multiple different settings for multiple different I/O circuit parameters, the test system sets a value for each I/O circuit parameter, generates test traffic to stress test the memory device with the parameter value(s), and measures an operating margin for the I/O performance characteristic. The test system further executes a search function to determine values for each I/O circuit parameter at which the operating margin meets a minimum threshold and performance of at least one of the I/O circuit parameters is increased. The memory subsystem sets runtime values for the I/O circuit parameters based on the search function.
摘要翻译：内存子系统通过内存设备经验性地测试I / O的性能参数。基于经验测试，存储器子系统可以设置特定于包含存储器子系统的系统的性能参数。测试系统执行测试。对于多个不同I / O电路参数的多个不同设置中的每一个，测试系统为每个I / O电路参数设置一个值，生成测试流量以用参数值对存储器件进行压力测试，并测量操作裕量为I / O性能特点。测试系统进一步执行搜索功能以确定每个I / O电路参数的值，在该参数下操作裕度满足最小阈值，并且至少一个I / O电路参数的性能提高。内存子系统根据搜索功能设置I / O电路参数的运行时间值。

7. 发明授权

US09514835B2 Determination of word line to word line shorts between adjacent blocks 有权
标题翻译：确定字线到相邻块之间的字线短路
公开(公告)号：US09514835B2
公开(公告)日：2016-12-06
申请号：US14328070
申请日：2014-07-10
申请人： SANDISK TECHNOLOGIES LLC
发明人： Sagar Magia , Jagdish Sabde , Khanh Nguyen
IPC分类号： G11C16/34 , G11C29/02 , G11C29/06 , H01L27/115 , G11C29/12
CPC分类号： G11C16/3422 , G11C16/0466 , G11C16/0483 , G11C16/16 , G11C29/025 , G11C29/06 , G11C2029/1202 , H01L27/1157 , H01L27/11582
摘要： A number of techniques for determining defects in non-volatile memory arrays are presented, which are particularly applicable to 3D NAND memory, such as that of the BiCS type. Word line to word shorts within a memory block are determined by application of an AC stress mode, followed by a defect detection operation. An inter-block stress and detection operation can be used determine word line to word line leaks between different blocks. Select gate leak line leakage, both the word lines and other select lines, is consider, as are shorts from word lines and select lines to local source lines. In addition to word line and select line defects, techniques for determining shorts between bit lines and low voltage circuitry, as in the sense amplifiers, are presented.
摘要翻译：提出了用于确定非易失性存储器阵列中的缺陷的许多技术，其特别适用于诸如BiCS类型的3D NAND存储器。通过应用AC应力模式，随后进行缺陷检测操作来确定存储器块内的字线到字短路。可以使用块间应力和检测操作来确定不同块之间的字线到字线泄漏。选择栅极泄漏线泄漏，字线和其他选择线都是考虑的，也是字线的短路，并选择线到本地源极线。除了字线和选择线缺陷之外，还提供了用于确定位线和低电压电路之间的短路的技术，如在读出放大器中。

8. 发明授权

US09502126B1 Memory system and operating method thereof 有权
标题翻译：存储系统及其操作方法
公开(公告)号：US09502126B1
公开(公告)日：2016-11-22
申请号：US15050650
申请日：2016-02-23
申请人： SK hynix Inc.
发明人： Dong Hyun Kim
IPC分类号： G11C29/06 , G11C29/50 , G11C16/26
CPC分类号： G11C16/26 , G06F11/1048 , G11C16/3454 , G11C29/021 , G11C29/028 , G11C29/06 , G11C29/52 , G11C2029/0411 , G11C2029/5004
摘要： A method of operating a semiconductor memory device includes applying a read voltage to a selected word line on which a program operation is performed; applying a first pass voltage to at least one unselected word line adjacent to the selected word line; applying a second pass voltage to the at least one unselected word line when a first reference time elapses; and performing a read operation on memory cells connected to the selected word line according to the read voltage when a second reference time elapses.
摘要翻译：一种操作半导体存储器件的方法包括：对所执行的编程操作的所选字线施加读取电压; 对与所选择的字线相邻的至少一个未选择的字线施加第一通过电压; 当经过第一参考时间时，向所述至少一个未选择字线施加第二通过电压; 并且当经过第二参考时间时，根据读取的电压对连接到所选字线的存储器单元执行读取操作。

9. 发明授权

US09455008B2 Word line test control circuit of semiconductor apparatus and testing method thereof 有权
标题翻译：半导体装置的字线测试控制电路及其测试方法
公开(公告)号：US09455008B2
公开(公告)日：2016-09-27
申请号：US14278432
申请日：2014-05-15
申请人： SK hynix Inc.
发明人： Don Hyun Choi
IPC分类号： G11C8/08 , G11C8/12 , G11C29/06 , G11C29/26 , G11C29/12
CPC分类号： G11C8/12 , G11C8/08 , G11C29/06 , G11C29/26 , G11C2029/1202 , G11C2029/2602
摘要： A semiconductor apparatus includes a plurality of memory blocks divided into an even mat group and an odd mat group; and an active control block configured to activate any one group of the even mat group and the odd mat group at a first timing in response to a plurality of test signals, and activate the other group at a second timing.
摘要翻译：半导体装置包括被分成偶数组和奇数组的多个存储块; 以及活动控制块，被配置为响应于多个测试信号在第一定时激活偶数组和奇数组的任何一组，并且在第二定时激活另一组。

10. 发明授权

US09335365B2 Split gate structure and method of using same 有权
公开(公告)号：US09335365B2
公开(公告)日：2016-05-10
申请号：US14724875
申请日：2015-05-29
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Yen-Chieh Huang , Ching-Huang Wang , Tsung-Yi Yu
IPC分类号： G01R31/02 , G01R31/26 , G11C29/48 , G11C16/04 , G11C29/00 , G11C29/06 , G11C29/56 , H01L21/66
CPC分类号： G01R31/2644 , G01R31/26 , G01R31/2601 , G01R31/2642 , G11C16/0425 , G11C29/006 , G11C29/06 , G11C29/48 , G11C29/56008 , H01L22/34
摘要： A method comprises providing first and second semiconductor devices. Each device comprises a transistor having a split gate electrode including first and second gate portions. Each device has a respective ratio between an area of its first gate portion and a sum of areas of its first and second gate portions. For each device, a stress voltage is applied to the first gate portion, but not to the second gate portion. For each device, the first and second gate portions are biased with a common voltage, and data are collected indicating a respective degradation for each device due to the stress voltage. The degradation has a component due to time dependent dielectric breakdown (TDDB) and a component due to bias temperature instability. From the collected data extrapolation determines the degradation component due to TDDB.

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