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31. 发明申请

US20120244668A1 SEMICONDUCTOR DEVICES WITH LAYOUT CONTROLLED CHANNEL AND ASSOCIATED PROCESSES OF MANUFACTURING 审中-公开
标题翻译：具有布局控制通道和相关制造工艺的半导体器件
公开(公告)号：US20120244668A1
公开(公告)日：2012-09-27
申请号：US13072569
申请日：2011-03-25
申请人： Jeesung Jung
发明人： Jeesung Jung
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L29/1066 , H01L29/66901
摘要： The present technology is directed generally to processes of forming semiconductor devices (e.g., JFET devices). The semiconductor device comprises a gate region, a source region, a drain region and a channel region having a channel size. The channel size is controlled by adjusting a layout width of the gate region.
摘要翻译：本技术一般涉及形成半导体器件（例如JFET器件）的工艺。半导体器件包括栅极区，源极区，漏极区和具有沟道尺寸的沟道区。通过调整栅极区域的布局宽度来控制通道尺寸。

32. 发明申请

US20120161208A1 Semiconductor Devices with Minimized Current Flow Differences and Methods of Same 有权
标题翻译：具有最小电流流动差异的半导体器件及其方法相同
公开(公告)号：US20120161208A1
公开(公告)日：2012-06-28
申请号：US12980005
申请日：2010-12-28
申请人： John V. Veliadis
发明人： John V. Veliadis
IPC分类号： H01L29/80 , H01L21/337
CPC分类号： H01L29/8083 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/66909
摘要： A semiconductor device with minimized current flow differences and method of fabricating same are disclosed. The method includes forming a semiconductor stack including a plurality of layers that include a first layer having a first conductivity type and a second layer having a first conductivity type, in which the second layer is on top of the first layer, forming a plurality of mesas in the semiconductor layer stack, and forming a plurality of gates in the semiconductor layer stack having a second conductivity type and situated partially at a periphery of the mesas, in which the plurality of gates are formed to minimize current flow differences between a current flowing from the first layer to the plurality of mesas at a first applied gate bias and a current flowing from the first layer to the plurality of mesas at a second applied gate bias when voltage is applied to the semiconductor device.
摘要翻译：公开了一种具有最小电流流动差的半导体器件及其制造方法。该方法包括形成包括多个层的半导体堆叠，所述多个层包括具有第一导电类型的第一层和具有第一导电类型的第二层，其中第二层位于第一层的顶部，形成多个台面在所述半导体层堆叠中，并且在所述半导体层堆叠中形成具有第二导电类型并且部分位于所述台面的周边的多个栅极，其中形成所述多个栅极以使流过当施加电压到半导体器件时，在第一施加的栅极偏压下的第一层到多个台面并且以第二施加的栅极偏压从第一层流向多个台的电流。

33. 发明申请

US20120091514A1 Semiconductor Junction Diode Device And Method For Manufacturing The Same 审中-公开
标题翻译：半导体结二极管器件及其制造方法
公开(公告)号：US20120091514A1
公开(公告)日：2012-04-19
申请号：US13377958
申请日：2011-02-27
申请人： Qingqing Liang , Huicai Zhong , Huilong Zhu
发明人： Qingqing Liang , Huicai Zhong , Huilong Zhu
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/8611 , H01L29/1602 , H01L29/1608 , H01L29/161 , H01L29/20 , H01L29/6603 , H01L29/6606 , H01L29/6609 , H01L29/66128 , H01L29/66204 , H01L29/861
摘要： A semiconductor junction diode device structure and a method for manufacturing the same are provided, where a gate of the diode device structure is directly formed on the substrate, a P-N junction is formed in the semiconductor substrate, a first contact is formed on the gate, and a second contact is formed on the doped region at both sides of the gate, the first contact and the second contact acting as cathode/anode of the diode device, respectively. The diode device of this structure occupies a small area, and its forming process may be integrated in a gate-last integration process of MOSFET devices, which needs no additional mask and costs and has a high integration level.
摘要翻译：提供一种半导体结二极管器件结构及其制造方法，其中二极管器件结构的栅极直接形成在衬底上，在该半导体衬底中形成PN结，在栅极上形成第一接触，并且第二接触形成在栅极两侧的掺杂区域上，第一接触和第二接触分别用作二极管器件的阴极/阳极。该结构的二极管器件占地面积小，其形成过程可集成在MOSFET器件的最终集成过程中，无需额外的掩模和成本，并具有较高的集成度。

34. 发明申请

US20110291107A1 SELF-ALIGNED SEMICONDUCTOR DEVICES WITH REDUCED GATE-SOURCE LEAKAGE UNDER REVERSE BIAS AND METHODS OF MAKING 有权
标题翻译：具有减少门极泄漏的自对准半导体器件，具有反向偏置和制造方法
公开(公告)号：US20110291107A1
公开(公告)日：2011-12-01
申请号：US13112075
申请日：2011-05-20
申请人： Andrew Ritenour , David C. Sheridan
发明人： Andrew Ritenour , David C. Sheridan
IPC分类号： H01L29/161 , H01L21/337 , H01L29/808
CPC分类号： H01L29/8083 , H01L29/0657 , H01L29/1066 , H01L29/1608 , H01L29/66068 , H01L29/66909 , H01L29/7722
摘要： A vertical junction field effect transistor (VJFET) having a self-aligned pin, a p+/n/n+ or a p+/p/n+ gate-source junction is described. The device gate can be self-aligned to within 0.5 μm to the source in order to maintain good high voltage performance (i.e. low DIBL) while reducing gate-source junction leakage under reverse bias. The device can be a wide-bandgap semiconductor device such as a SiC vertical channel junction field effect. Methods of making the device are also described.
摘要翻译：描述了具有自对准引脚，p + / n / n +或p + / p / n +栅 - 源极结的垂直结型场效应晶体管（VJFET）。为了保持良好的高电压性能（即低DIBL），器件栅极可以自对准至0.5μm以内，同时减少反向偏压下的栅 - 源结泄漏。该器件可以是宽带隙半导体器件，例如SiC垂直沟道结场效应。还描述了制造该装置的方法。

35. 发明申请

US20110227093A1 FIELD EFFECT TRANSISTOR AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：场效应晶体管及其制造方法
公开(公告)号：US20110227093A1
公开(公告)日：2011-09-22
申请号：US13150574
申请日：2011-06-01
申请人： Masahiro HIKITA , Hidetoshi ISHIDA , Tetsuzo UEDA
发明人： Masahiro HIKITA , Hidetoshi ISHIDA , Tetsuzo UEDA
IPC分类号： H01L29/20 , H01L21/337 , H01L29/808
CPC分类号： H01L29/7786 , H01L29/1066 , H01L29/2003 , H01L29/205 , H01L29/41766 , H01L29/66462 , H01L29/808
摘要： The present invention has an object to provide an FET and a method of manufacturing the FET that are capable of increasing the threshold voltage as well as decreasing the on-resistance. The FET of the present invention includes a first undoped GaN layer; a first undoped AlGaN layer formed on the first undoped GaN layer, having a band gap energy greater than that of the first undoped GaN layer; a second undoped GaN layer formed on the first undoped AlGaN layer; a second undoped AlGaN layer formed on the second undoped GaN layer, having a band gap energy greater than that of the second undoped GaN layer; a p-type GaN layer formed in the recess of the second undoped AlGaN layer; a gate electrode formed on the p-type GaN layer; and a source electrode and a drain electrode which are formed in both lateral regions of the gate electrode, wherein a channel is formed at the heterojunction interface between the first undoped GaN layer and the first undoped AlGaN layer.
摘要翻译：本发明的目的是提供一种能够增加阈值电压以及降低导通电阻的FET和FET的制造方法。本发明的FET包括第一未掺杂的GaN层; 形成在第一未掺杂的GaN层上的第一未掺杂的AlGaN层，其带隙能量大于第一未掺杂的GaN层的带隙能量; 形成在第一未掺杂的AlGaN层上的第二未掺杂的GaN层; 形成在所述第二未掺杂GaN层上的第二未掺杂AlGaN层，具有大于所述第二未掺杂GaN层的带隙能量的带隙能量; 形成在第二未掺杂AlGaN层的凹部中的p型GaN层; 形成在p型GaN层上的栅电极; 以及形成在所述栅电极的两个横向区域中的源电极和漏电极，其中在所述第一未掺杂的GaN层和所述第一未掺杂的AlGaN层之间的异质结界面处形成沟道。

36. 发明申请

US20110212583A1 Method For Providing Semiconductors Having Self-Aligned Ion Implant 有权
标题翻译：提供具有自对准离子植入物的半导体的方法
公开(公告)号：US20110212583A1
公开(公告)日：2011-09-01
申请号：US13078510
申请日：2011-04-01
申请人： Philip G. Neudeck
发明人： Philip G. Neudeck
IPC分类号： H01L21/337
CPC分类号： H01L29/808 , H01L21/046 , H01L21/0465 , H01L21/0475 , H01L21/26593 , H01L29/0843 , H01L29/1602 , H01L29/1608 , H01L29/2003 , H01L29/66068 , H01L29/66901 , H01L29/66916
摘要： A method is disclosed that provides a self-aligned nitrogen-implant particularly suited for a Junction Field Effect Transistor (JFET) semiconductor device preferably comprised of a silicon carbide (SiC). This self-aligned nitrogen-implant allows for the realization of durable and stable electrical functionality of high temperature transistors such as JFETs. The method implements the self-aligned nitrogen-implant having predetermined dimensions, at a particular step in the fabrication process, so that the SiC junction field effect transistors are capable of being electrically operating continuously at 500° C. for over 10,000 hours in an air ambient with less than a 10% change in operational transistor parameters.
摘要翻译：公开了一种提供特别适合于优选由碳化硅（SiC）构成的结型场效应晶体管（JFET）半导体器件的自对准氮注入的方法。这种自对准氮 - 注入允许实现高温晶体管（例如JFET）的耐用且稳定的电功能。该方法在制造过程的特定步骤中实现具有预定尺寸的自对准氮注入，使得SiC结场效应晶体管能够在500℃下连续电连续工作，在空气中超过10,000小时环境中运行晶体管参数的变化小于10％。

37. 发明授权

US07977714B2 Wrapped gate junction field effect transistor 有权
标题翻译：封装栅结场效应晶体管
公开(公告)号：US07977714B2
公开(公告)日：2011-07-12
申请号：US11875190
申请日：2007-10-19
申请人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
发明人： John Ellis-Monaghan , Richard A. Phelps , Robert M. Rassel , Steven H. Voldman , Michael J. Zierak
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/808 , H01L29/1058 , H01L29/1066 , H01L29/1608 , H01L29/20 , H01L29/22 , H01L29/66901 , H01L29/66924
摘要： A wrapped gate junction field effect transistor (JFET) with at least one semiconductor channel having a first conductivity type doping is provided. Both sidewalls of each of the at least one semiconductor channel laterally abuts a side gate region having a second conductivity type doping, which is the opposite of the first conductivity doping. Further, the at least one semiconductor channel vertically abuts a top gate region and at least one bottom gate region, both having the second conductivity type doping. The gate electrode, which comprises side gate region, the top gate region, and at least one bottom gate regions, wraps around each of the at least one semiconductor channel to provide tight control of the current, i.e., a low off-current, through the at least one semiconductor channel. By employing multiple channels, the JFET may provide a high on-current.
摘要翻译：提供具有至少一个具有第一导电类型掺杂的半导体沟道的封装的栅极结场效应晶体管（JFET）。所述至少一个半导体通道中的每一个的两个侧壁横向邻接具有第二导电类型掺杂的侧栅极区域，其与第一导电掺杂相反。此外，至少一个半导体沟道垂直邻接顶部栅极区域和至少一个具有第二导电类型掺杂的底部栅极区域。包括侧栅极区域的栅极电极，顶栅极区域和至少一个底栅极区域围绕至少一个半导体通道中的每一个环绕，以提供电流的严格控制，即，低截止电流，通过所述至少一个半导体通道。通过采用多个通道，JFET可以提供高导通电流。

38. 发明申请

US20110156054A1 SILICON CARBIDE SEMICONDUCTOR DEVICE AND METHOD OF MANUFACTURING THE SAME 有权
标题翻译：硅碳化硅半导体器件及其制造方法
公开(公告)号：US20110156054A1
公开(公告)日：2011-06-30
申请号：US12976116
申请日：2010-12-22
申请人： Yuuichi TAKEUCHI , Rajesh Kumar Malhan , Naohiro Sugiyama
发明人： Yuuichi TAKEUCHI , Rajesh Kumar Malhan , Naohiro Sugiyama
IPC分类号： H01L29/24 , H01L21/337 , H01L21/336
CPC分类号： H01L29/0847 , H01L29/0696 , H01L29/1608 , H01L29/66068 , H01L29/7828
摘要： A silicon carbide semiconductor device having a JFET or a MOSFET includes a semiconductor substrate and a trench. The semiconductor substrate has a silicon carbide substrate, a drift layer on the silicon carbide substrate, a first gate region on the drift layer, and a source region on the first gate region. The trench has a strip shape with a longitudinal direction and reaches the drift layer by penetrating the source region and the first gate region. The trench is filled with a channel layer and a second gate region on the channel layer. The source region is not located at an end portion of the trench in the longitudinal direction.
摘要翻译：具有JFET或MOSFET的碳化硅半导体器件包括半导体衬底和沟槽。半导体衬底具有碳化硅衬底，碳化硅衬底上的漂移层，漂移层上的第一栅极区域和第一栅极区域上的源极区域。沟槽具有纵向方向的带状，并通过穿透源极区域和第一栅极区域而到达漂移层。在沟道层上填充沟道层和第二栅极区域。源极区域不位于沟槽的纵向方向的端部。

39. 发明申请

US20110156052A1 Semiconductor device having JFET and method for manufacturing the same 审中-公开
标题翻译：具有JFET的半导体器件及其制造方法
公开(公告)号：US20110156052A1
公开(公告)日：2011-06-30
申请号：US12926894
申请日：2010-12-16
申请人： Rajesh Kumar Malhan , Yuuichi Takeuchi , Naohiro Sugiyama
发明人： Rajesh Kumar Malhan , Yuuichi Takeuchi , Naohiro Sugiyama
IPC分类号： H01L29/24 , H01L29/80 , H01L21/337
CPC分类号： H01L29/808 , H01L29/045 , H01L29/1066 , H01L29/1608 , H01L29/66068
摘要： A semiconductor device having a JFET includes: a substrate made of semi-insulating semiconductor material; a gate region in a surface portion of the substrate; a channel region disposed on and contacting the gate region; a source region and a drain region disposed on both sides of the gate region so as to sandwich the channel region, respectively; a source electrode electrically coupled with the source region; a drain electrode electrically coupled with the drain region; and a gate electrode electrically coupled with the gate region. An impurity concentration of each of the source region and the drain region is higher than an impurity concentration of the channel region.
摘要翻译：具有JFET的半导体器件包括：由半绝缘半导体材料制成的衬底; 在所述基板的表面部分中的栅极区域; 设置在栅区上并与其接触的沟道区; 源极区域和漏极区域，分别设置在栅极区域的两侧，以夹持沟道区域; 源极，与源极电耦合; 漏极，与漏极区电耦合; 以及与栅极区域电耦合的栅电极。源极区域和漏极区域中的每一个的杂质浓度高于沟道区域的杂质浓度。

40. 发明申请

US20110133212A1 METHODS OF MAKING SEMICONDUCTOR DEVICES HAVING IMPLANTED SIDEWALLS AND DEVICES MADE THEREBY 有权
标题翻译：制造具有嵌入式半导体器件的半导体器件的方法及其器件
公开(公告)号：US20110133212A1
公开(公告)日：2011-06-09
申请号：US12962823
申请日：2010-12-08
申请人： David C. SHERIDAN , Andrew RITENOUR
发明人： David C. SHERIDAN , Andrew RITENOUR
IPC分类号： H01L29/808 , H01L21/337
CPC分类号： H01L29/8083 , H01L21/047 , H01L29/1066 , H01L29/1608 , H01L29/66068
摘要： Semiconductor devices and methods of making the devices are described. The devices can be junction field-effect transistors (JFETs) or diodes such as junction barrier Schottky (JBS) diodes or PiN diodes. The devices are made using selective ion implantation using an implantation mask. The devices have implanted sidewalls formed by scattering of normal or near normal incident ions from the implantation mask. Vertical junction field-effect transistors with long channel length are also described. The devices can be made from a wide-bandgap semiconductor material such as silicon carbide (SiC) and can be used in high temperature and high power applications.
摘要翻译：对半导体装置及其制造方法进行说明。器件可以是结型场效应晶体管（JFET）或二极管，例如结型势垒肖特基（JBS）二极管或PiN二极管。使用注入掩模使用选择性离子注入制造器件。器件具有通过从注入掩模中散射正常或接近正常的入射离子而形成的侧壁。还描述了具有长沟道长度的垂直结型场效应晶体管。这些器件可以由诸如碳化硅（SiC）的宽带隙半导体材料制成，并且可以用于高温和高功率应用中。

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