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1. 发明申请

US20180350901A1 SEMICONDUCTOR DEVICE AND METHOD FOR PRODUCING SEMICONDUCTOR DEVICE 审中-公开
公开(公告)号：US20180350901A1
公开(公告)日：2018-12-06
申请号：US16048509
申请日：2018-07-30
申请人： FUJI ELECTRIC CO., LTD.
发明人： Takashi YOSHIMURA , Masayuki MIYAZAKI , Hiroshi TAKISHITA , Hidenao KURIBAYASHI
IPC分类号： H01L29/06 , H01L29/10 , H01L21/263 , H01L21/265 , H01L21/324 , H01L29/08 , H01L29/32 , H01L29/36 , H01L29/66 , H01L29/739 , H01L29/861
CPC分类号： H01L29/063 , H01L21/263 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/0619 , H01L29/0834 , H01L29/1095 , H01L29/32 , H01L29/36 , H01L29/66128 , H01L29/7395 , H01L29/861 , H01L29/8611
摘要： Hydrogen atoms and crystal defects are introduced into an n-semiconductor substrate by proton implantation. The crystal defects are generated in the n-semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.

2. 发明授权

US10038071B2 Semiconductor device and method for manufacturing semiconductor device 有权
公开(公告)号：US10038071B2
公开(公告)日：2018-07-31
申请号：US15410304
申请日：2017-01-19
申请人： ROHM CO., LTD. , LAPIS Semiconductor Co., Ltd.
发明人： Akihiro Hikasa , Kazusuke Kato
IPC分类号： H01L33/00 , H01L29/45 , H01L29/16 , H01L29/861 , H01L29/739 , H01L29/78 , H01L29/732 , H01L21/04 , H01L21/3205 , H01L21/02 , H01L21/3213
CPC分类号： H01L29/45 , H01L21/02244 , H01L21/0485 , H01L21/32051 , H01L21/32134 , H01L23/53223 , H01L29/0615 , H01L29/0619 , H01L29/0638 , H01L29/16 , H01L29/1608 , H01L29/401 , H01L29/404 , H01L29/41708 , H01L29/41725 , H01L29/42304 , H01L29/456 , H01L29/66068 , H01L29/66128 , H01L29/66712 , H01L29/66734 , H01L29/732 , H01L29/7395 , H01L29/7397 , H01L29/7802 , H01L29/7811 , H01L29/7813 , H01L29/861 , H01L29/8611
摘要： A semiconductor device according to the present invention includes: a semiconductor layer including a first conductivity type semiconductor region and a second conductivity type semiconductor region joined to the first conductivity type semiconductor region; and a surface electrode connected to the second conductivity type region on one surface of the semiconductor layer, including a first Al-based electrode, a second Al-based electrode, an Al-based oxide film interposed between the first Al-based electrode and the second Al-based electrode, and a plated layer on the second Al-based electrode.

3. 发明申请

US20180061982A1 AN ELECTRONIC JUNCTION DEVICE WITH A REDUCED RECOVERY TIME FOR APPLICATIONS SUBJECT TO THE CURRENT RECIRCULATION PHENOMENON AND RELATED MANUFACTURING PROCESS 审中-公开
公开(公告)号：US20180061982A1
公开(公告)日：2018-03-01
申请号：US15457799
申请日：2017-03-13
申请人： STMICROELECTRONICS S.R.L.
发明人： Marco Sambi , Fabrizio Fausto Renzo Toia , Marco Marchesi , Marco Morelli , Riccardo Depetro , Giuseppe Barillaro , Lucanos Marsilio Strambini
IPC分类号： H01L29/78 , H01L29/06 , H01L29/417 , H01L29/36 , H01L29/66 , H01L21/3063 , H01L21/265 , H01L21/308 , H01L21/02 , H01L29/08 , H01L21/762 , H03K17/687
CPC分类号： H01L29/7827 , H01L21/02233 , H01L21/02255 , H01L21/26513 , H01L21/3063 , H01L21/3081 , H01L21/76224 , H01L29/0649 , H01L29/0653 , H01L29/0665 , H01L29/0847 , H01L29/16 , H01L29/32 , H01L29/36 , H01L29/41741 , H01L29/66128 , H01L29/66666 , H01L29/66681 , H01L29/7816 , H01L29/8611 , H03K17/687
摘要： An integrated electronic device having a semiconductor body including: a first electrode region having a first type of conductivity; and a second electrode region having a second type of conductivity, which forms a junction with the first electrode region. The integrated electronic device further includes a nanostructured semiconductor region, which extends in one of the first and second electrode regions.

4. 发明授权

US09899470B2 Method for forming a power semiconductor device and a power semiconductor device 有权
公开(公告)号：US09899470B2
公开(公告)日：2018-02-20
申请号：US15597194
申请日：2017-05-17
申请人： Infineon Technologies Austria AG
发明人： Marko Lemke , Knut Stahrenberg , Ralf Rudolf , Rolf Weis
IPC分类号： H01L29/06 , H01L21/762 , H01L21/265 , H01L21/306 , H01L29/66 , H01L27/06 , H01L27/085
CPC分类号： H01L29/0634 , H01L21/223 , H01L21/2255 , H01L21/2257 , H01L21/26506 , H01L21/2652 , H01L21/30604 , H01L21/76224 , H01L27/0629 , H01L27/085 , H01L29/0649 , H01L29/0692 , H01L29/1608 , H01L29/2003 , H01L29/6606 , H01L29/6609 , H01L29/66128 , H01L29/66204 , H01L29/66477 , H01L29/8611
摘要： A method of forming a power semiconductor device includes providing a semiconductor layer of a first conductivity type extending to a first side and having a first doping concentration of first dopants providing majority charge carriers of a first electric charge type in the layer, and forming a deep trench isolation including forming a trench which extends from the first side into the semiconductor layer and includes, in a vertical cross-section perpendicular to the first side, a wall, forming a compensation semiconductor region of the first conductivity type at the wall and having a second doping concentration of the first dopants higher than the first doping concentration, and filling the trench with a dielectric material. The amount of first dopants in the compensation semiconductor region is such that a field-effect of fixed charges of the first electric charge type which are trapped in the trench is at least partly compensated.

5. 发明申请

US20170271438A1 METHOD OF PRODUCING SEMICONDUCTOR CHIPS 审中-公开
公开(公告)号：US20170271438A1
公开(公告)日：2017-09-21
申请号：US15614917
申请日：2017-06-06
申请人： OSRAM Opto Semiconductors GmbH
发明人： Ewald Karl Michael Günther , Andreas Plössl , Heribert Zull , Thomas Veit , Mathias Kämpf , Jens Dennemarck , Bernd Böhm , Korbinian Perzlmaier
IPC分类号： H01L29/06 , H01L25/16 , H01L29/66 , H01L27/02 , H01L27/14 , H01L27/15 , H01L33/00 , H01L33/64 , H01L33/38 , H01L23/60
CPC分类号： H01L29/0607 , H01L23/60 , H01L25/167 , H01L27/0248 , H01L27/14 , H01L27/15 , H01L29/66128 , H01L33/0079 , H01L33/382 , H01L33/641 , H01L2224/48247 , H01L2224/49107 , H01L2224/73265
摘要： A method of producing a plurality of semiconductor chips includes a) providing a carrier substrate having a first major face and a second major face opposite the first major face; b) forming a diode structure between the first major face and the second major face, the diode structure electrically insulating the first major face from the second major face at least with regard to one polarity of an electrical voltage; c) arranging a semiconductor layer sequence on the first major face of the carrier substrate; and d) singulating the carrier substrate with the semiconductor layer sequence into a plurality of semiconductor chips.

6. 发明授权

US09768246B2 Semiconductor device and method for producing semiconductor device 有权
公开(公告)号：US09768246B2
公开(公告)日：2017-09-19
申请号：US15008826
申请日：2016-01-28
申请人： FUJI ELECTRIC CO., LTD.
发明人： Takashi Yoshimura , Masayuki Miyazaki , Hiroshi Takishita , Hidenao Kuribayashi
IPC分类号： H01L21/04 , H01L21/425 , H01L21/265 , H01L29/30 , H01L29/06 , H01L29/32 , H01L29/36 , H01L29/66 , H01L29/739 , H01L29/861 , H01L29/08 , H01L21/263 , H01L29/10 , H01L21/324
CPC分类号： H01L29/063 , H01L21/263 , H01L21/26506 , H01L21/26513 , H01L21/324 , H01L29/0619 , H01L29/0834 , H01L29/1095 , H01L29/32 , H01L29/36 , H01L29/66128 , H01L29/7395 , H01L29/861 , H01L29/8611
摘要： Hydrogen atoms and crystal defects are introduced into an n− semiconductor substrate by proton implantation. The crystal defects are generated in the n− semiconductor substrate by electron beam irradiation before or after the proton implantation. Then, a heat treatment for generating donors is performed. The amount of crystal defects is appropriately controlled during the heat treatment for generating donors to increase a donor generation rate. In addition, when the heat treatment for generating donors ends, the crystal defects formed by the electron beam irradiation and the proton implantation are recovered and controlled to an appropriate amount of crystal defects. Therefore, for example, it is possible to improve a breakdown voltage and reduce a leakage current.

7. 发明授权

US09767915B2 One-time programmable device with integrated heat sink 有权
公开(公告)号：US09767915B2
公开(公告)日：2017-09-19
申请号：US15297922
申请日：2016-10-19
申请人： Attopsemi Technology Co., LTD
发明人： Shine C. Chung
IPC分类号： G11C17/16 , G11C17/06 , G11C13/00 , G11C7/22 , H01L29/66 , H01L29/861 , H01L29/06 , G11C17/18 , H01L23/525 , H01L27/102 , H01L27/112 , G11C11/16 , G11C17/02 , H01L29/732
CPC分类号： G11C17/06 , G11C7/222 , G11C11/16 , G11C11/161 , G11C11/1659 , G11C11/1673 , G11C11/1675 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0011 , G11C13/003 , G11C13/0038 , G11C13/004 , G11C17/02 , G11C17/16 , G11C17/165 , G11C17/18 , G11C2013/0054 , G11C2213/72 , G11C2213/74 , H01L23/5256 , H01L27/1021 , H01L27/11206 , H01L29/0649 , H01L29/66128 , H01L29/66136 , H01L29/732 , H01L29/861 , H01L29/8611 , H01L2924/0002 , H01L2924/00
摘要： Junction diodes fabricated in standard CMOS logic processes can be used as program selectors with at least one heat sink or heater to assist programming for One-Time Programmable (OTP) devices, such as electrical fuse, contact/via fuse, contact/via anti-fuse, or gate-oxide breakdown anti-fuse, etc. The heat sink can be at least one thin oxide area, extended OTP element area, or other conductors coupled to the OTP element to assist programming. A heater can be at least one high resistance area such as an unsilicided polysilicon, unsilicided active region, contact, via, or combined in serial, or interconnect to generate heat to assist programming. The OTP device has at least one OTP element coupled to at least one diode in a memory cell. The diode can be constructed by P+ and N+ active regions in a CMOS N well, or on an isolated active region as the P and N terminals of the diode. The isolation between P+ and the N+ active regions of the diode in a cell or between cells can be provided by dummy MOS gate, SBL, or STI/LOCOS isolations. The OTP element can be polysilicon, silicided polysilicon, silicide, polymetal, metal, metal alloy, local interconnect, metal-0, thermally isolated active region, CMOS gate, or combination thereof.

8. 发明授权

US09666699B1 Semiconductor device having field plate disposed on isolation feature and method for forming the same 有权
公开(公告)号：US09666699B1
公开(公告)日：2017-05-30
申请号：US15085219
申请日：2016-03-30
申请人： Vanguard International Semiconductor Corporation
发明人： Pei-Heng Hung , Manoj Kumar , Hsiung-Shih Chang , Chia-Hao Lee , Jun-Wei Chen
IPC分类号： H01L29/735 , H01L29/73 , H01L29/06 , H01L29/417 , H01L29/66 , H01L21/8222 , H01L21/762 , H01L29/423 , H01L29/40 , H01L29/861
CPC分类号： H01L29/7302 , H01L21/76264 , H01L21/8222 , H01L29/0649 , H01L29/402 , H01L29/41708 , H01L29/42304 , H01L29/6609 , H01L29/66128 , H01L29/66136 , H01L29/6625 , H01L29/735 , H01L29/861 , H01L29/8611
摘要： The invention provides a semiconductor device, including a buried oxide layer disposed on a substrate. A semiconductor layer is disposed on the buried oxide layer. A first well is disposed in the semiconductor layer. A second well and a third well are disposed to opposite sides of the first well and separated from the first well. An isolation feature covers the first well and the third well. A poly field plate is disposed on the isolation feature and over the semiconductor layer between the first well and the third well. A first anode doped region is disposed on the second well. A second anode doped region and a third anode doped region are disposed on the second well. The second anode doped region is positioned directly on the third anode doped region. A first cathode doped region is coupled to the third well.

9. 发明申请

US20170092714A1 METHOD OF MANUFACTURING SEMICONDUCTOR DEVICE AND SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20170092714A1
公开(公告)日：2017-03-30
申请号：US15307608
申请日：2015-04-20
申请人： TOYOTA JIDOSHA KABUSHIKI KAISHA
发明人： Yuki HORIUCHI , Satoru KAMEYAMA
IPC分类号： H01L29/06 , H01L29/861 , H01L21/225 , H01L21/265 , H01L21/324
CPC分类号： H01L29/063 , H01L21/2253 , H01L21/26513 , H01L21/268 , H01L21/324 , H01L29/36 , H01L29/66128 , H01L29/861 , H01L29/8611
摘要： A structure having high, middle, and low impurity concentration regions disposed from a surface side of a substrate is more suitably manufactured. A method of manufacturing a semiconductor device includes: a first implantation of first conductivity type impurities into a first conductivity type semiconductor substrate from a surface; melting and solidifying a first semiconductor region between a depth and the surface, wherein the depth is deeper than a depth having a peak impurity concentration in an increased region where the impurity concentration was increased in the first implantation, and shallower than a deeper end of the increased region; a second implantation of the impurities from the surface into a region shallower than the depth; and melting and solidifying a region in which the impurity concentration was increased in the second implantation.

10. 发明申请

US20170062431A1 METHOD OF FORMING A JUNCTION FIELD EFFECT TRANSISTOR 有权
标题翻译：形成场效应晶体管的方法
公开(公告)号：US20170062431A1
公开(公告)日：2017-03-02
申请号：US15245671
申请日：2016-08-24
申请人： IMEC VZW
发明人： Geert Hellings , Geert Van der Plas , Mirko Scholz
IPC分类号： H01L27/092 , H01L21/266 , H01L27/06 , H01L21/033 , H01L29/808 , H01L29/66
CPC分类号： H01L27/0928 , H01L21/0332 , H01L21/265 , H01L21/266 , H01L21/761 , H01L27/0629 , H01L27/098 , H01L29/1058 , H01L29/456 , H01L29/66128 , H01L29/66893 , H01L29/66901 , H01L29/808 , H01L29/8611
摘要： The disclosed technology relates to semiconductors, and more particularly to a junction field effect transistor (JFET). In one aspect, a method of fabricating a JFET includes forming a well of a first dopant type in a substrate, wherein the well is isolated from the substrate by an isolation region of a second dopant type. The method additionally includes implanting a dopant of the second dopant type at a surface of the well to form a source, a drain and a channel of the JFET, and implanting a dopant of the first dopant type at the surface of the well to form a gate of the JFET. The method additionally includes, prior to implanting the dopant of the first type and the dopant of the second type, forming a pre-metal dielectric (PMD) layer on the well and forming contact openings in the PMD layer above the source, the drain and the gate. The PMD layer has a thickness such that the channel is formed by implanting the dopant of the first type and the dopant of the second type through the PMD layer. The method further includes, after implanting the dopant of the first type and the dopant of the second type, siliciding the source, the drain and the gate, and forming metal contacts in the contact openings.
摘要翻译：所公开的技术涉及半导体，更具体地涉及结型场效应晶体管（JFET）。一方面，一种制造JFET的方法包括在衬底中形成第一掺杂剂阱，其中阱通过第二掺杂剂类型的隔离区与衬底隔离。该方法另外包括在阱的表面处注入第二掺杂剂类型的掺杂剂以形成JFET的源极，漏极和沟道，以及在阱的表面处注入第一掺杂剂类型的掺杂剂，以形成 JFET栅极。该方法还包括在植入第一类型的掺杂剂和第二类型的掺杂剂之前，在阱上形成预金属电介质（PMD）层并在源上形成PMD层中的接触开口，漏极和大门。 PMD层的厚度使得通过PMD层注入第一类掺杂剂和第二类掺杂剂形成沟道。该方法还包括在注入第一类型的掺杂剂和第二类型的掺杂剂之后，将源极，漏极和栅极硅化，并在接触开口中形成金属接触。

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