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31. 发明授权

US08445335B2 Method of forming pixel structure 有权
标题翻译：形成像素结构的方法
公开(公告)号：US08445335B2
公开(公告)日：2013-05-21
申请号：US13563766
申请日：2012-08-01
申请人： Jing-Tin Kuo , Che-Chia Hsu , Chao-Liang Lu
发明人： Jing-Tin Kuo , Che-Chia Hsu , Chao-Liang Lu
IPC分类号： H01L21/335
CPC分类号： G02F1/13624 , G02F2001/134345 , H01L27/124
摘要： A method of forming a pixel structure is provided. A pixel electrode made of transparent conductive material is formed to electrically connect a data line and a source electrode of a switching element of the adjacent sub-pixel region so that a plurality of sub-pixels can share the same data line. The number of data lines can be reduced, and the aperture ratio (AR) can be improved.
摘要翻译：提供一种形成像素结构的方法。形成由透明导电材料制成的像素电极，用于将相邻子像素区域的开关元件的数据线和源电极电连接，使得多个子像素可以共享相同的数据线。可以减少数据线的数量，并且可以提高开口率（AR）。

32. 发明申请

US20130119440A1 BIOSENSORS INTEGRATED WITH A MICROFLUIDIC STRUCTURE 有权
标题翻译：生物传感器与微流体结构集成
公开(公告)号：US20130119440A1
公开(公告)日：2013-05-16
申请号：US13293795
申请日：2011-11-10
申请人： Kristin M. ACKERSON , John J. ELLIS-MONAGHAN , Jeffrey P. GAMBINO , Yen L. LIM
发明人： Kristin M. ACKERSON , John J. ELLIS-MONAGHAN , Jeffrey P. GAMBINO , Yen L. LIM
IPC分类号： H01L29/772 , H01L21/335
CPC分类号： G01N27/4145 , H01L29/772
摘要： A biosensor with a microfluidic structure surrounded by an electrode and methods of forming the electrode around the microfluidic structure of the biosensor are provided. A method includes forming a gate or electrode in a first layer. The method further includes forming a trench in a second layer. The method further includes forming a first metal layer in the trench such that the first metal layer is in electrical contact with the gate or the electrode. The method further includes forming a sacrificial material in the trench. The method further includes forming a second metal layer over the sacrificial material and in contact with the first metal layer. The method further includes removing the sacrificial material such that a microfluidic channel is formed surrounded by the first and the second metal layers.
摘要翻译：提供了由电极包围的微流体结构的生物传感器和围绕生物传感器的微流体结构形成电极的方法。一种方法包括在第一层中形成栅极或电极。该方法还包括在第二层中形成沟槽。该方法还包括在沟槽中形成第一金属层，使得第一金属层与栅极或电极电接触。该方法还包括在沟槽中形成牺牲材料。该方法还包括在牺牲材料上形成第二金属层并与第一金属层接触。该方法还包括去除牺牲材料，使得由第一和第二金属层围绕的微流体通道形成。

33. 发明申请

US20130112986A1 Gallium Nitride Semiconductor Devices and Method Making Thereof 有权
标题翻译：氮化镓半导体器件及其制造方法
公开(公告)号：US20130112986A1
公开(公告)日：2013-05-09
申请号：US13292487
申请日：2011-11-09
申请人： Chih-Wen Hsiung , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chun-Wei Hsu , Chen-Ju Yu , Fu-Chih Yang
发明人： Chih-Wen Hsiung , Jiun-Lei Jerry Yu , Fu-Wei Yao , Chun-Wei Hsu , Chen-Ju Yu , Fu-Chih Yang
IPC分类号： H01L29/205 , H01L21/335 , B82Y99/00 , B82Y40/00
CPC分类号： H01L29/66462 , H01L29/1066 , H01L29/2003 , H01L29/7787
摘要： The present disclosure relates to an enhancement mode gallium nitride (GaN) transistor device. The GaN transistor device has an electron supply layer located on top of a GaN layer. An etch stop layer (e.g., AlN) is disposed above the electron supply layer. A gate structure is formed on top of the etch stop layer, such that the bottom surface of the gate structure is located vertically above the etch stop layer. The position of etch stop layer in the GaN transistor device stack allows it to both enhance gate definition during processing (e.g., selective etching of the gate structure located on top of the AlN layer) and to act as a gate insulator that reduces gate leakage of the GaN transistor device.
摘要翻译：本发明涉及增强型氮化镓（GaN）晶体管器件。 GaN晶体管器件具有位于GaN层顶部的电子供应层。蚀刻停止层（例如，AlN）设置在电子供应层上方。栅极结构形成在蚀刻停止层的顶部，使得栅极结构的底表面垂直位于蚀刻停止层上方。 GaN晶体管器件堆叠中的蚀刻停止层的位置允许其在处理期间增强栅极定义（例如，选择性蚀刻位于AlN层顶部的栅极结构），并且用作栅极绝缘体，以减小栅极泄漏 GaN晶体管器件。

34. 发明申请

US20130082305A1 STRUCTURE OF A HIGH ELECTRON MOBILITY TRANSISTOR AND A FABRICATION METHOD THEREOF 有权
标题翻译：高电子晶体管的结构及其制造方法
公开(公告)号：US20130082305A1
公开(公告)日：2013-04-04
申请号：US13339055
申请日：2011-12-28
申请人： Cheng-Guan YUAN , Shih-Ming Joseph Liu
发明人： Cheng-Guan YUAN , Shih-Ming Joseph Liu
IPC分类号： H01L29/778 , H01L21/335
CPC分类号： H01L29/42316 , H01L29/66462 , H01L29/7783
摘要： An improved structure of the high electron mobility transistor (HEMT) and a fabrication method thereof are disclosed. The improved HEMT structure comprises a substrate, a channel layer, a spacing layer, a carrier supply layer, a Schottky layer, a first etch stop layer, a first n type doped layer formed by AlxGa1-xAs, and a second n type doped layer. The fabrication method comprises steps of: etching a gate, a drain, and a source recess by using a multiple selective etching process. Below the gate, the drain, and the source recess is the Schottky layer. A gate electrode is deposited in the gate recess to form Schottky contact. A drain electrode and a source electrode are deposited to form ohmic contacts in the drain recess and the source recess respectively, and on the second n type doped layer surrounding the drain recess and the source recess respectively.
摘要翻译：公开了高电子迁移率晶体管（HEMT）的改进结构及其制造方法。改进的HEMT结构包括衬底，沟道层，间隔层，载流子供应层，肖特基层，第一蚀刻停止层，由Al x Ga 1-x As形成的第一n型掺杂层和第二n型掺杂层。该制造方法包括以下步骤：通过使用多重选择性蚀刻工艺蚀刻栅极，漏极和源极凹陷。在栅极下方，漏极和源极凹槽是肖特基层。栅电极沉积在栅极凹槽中以形成肖特基接触。沉积漏电极和源极以分别在漏极凹部和源极凹槽中以及在漏极凹部和源极凹槽周围的第二n型掺杂层上形成欧姆接触。

35. 发明申请

US20130062667A1 ENHANCEMENT/DEPLETION PHEMT DEVICE AND MANUFACTURING METHOD THEREOF 有权
标题翻译：增强/删除设备及其制造方法
公开(公告)号：US20130062667A1
公开(公告)日：2013-03-14
申请号：US13561860
申请日：2012-07-30
申请人： Alessandro CHINI , Claudio LANZIERI
发明人： Alessandro CHINI , Claudio LANZIERI
IPC分类号： H01L27/088 , H01L21/335
CPC分类号： H01L27/0605 , H01L21/8252 , H01L27/0883 , H01L27/095 , H01L29/66545
摘要： An embodiment of the present invention concerns a layered epitaxial structure for enhancement/depletion PHEMT devices, an enhancement/depletion PHEMT device and a method for manufacturing an enhancement/depletion PHEMT device that finds advantageous, but not exclusive, application in the manufacturing of integrated circuits operating at millimetre-wave and microwave frequencies.
摘要翻译：本发明的一个实施例涉及用于增强/消耗PHEMT器件的分层外延结构，增强/耗尽PHEMT器件和用于制造增强/消耗PHEMT器件的方法，其在集成电路的制造中发现有利但非排他的应用以毫米波和微波频率运行。

36. 发明授权

US08373206B2 Biosensor apparatuses and methods thereof 有权
标题翻译：生物传感器装置及其方法
公开(公告)号：US08373206B2
公开(公告)日：2013-02-12
申请号：US12839968
申请日：2010-07-20
申请人： Michael Potter
发明人： Michael Potter
IPC分类号： H01L29/66 , H01L21/335
CPC分类号： G01N33/54373 , G01N27/4145 , H01L29/66
摘要： A biosensor has one or more field effect transistors each comprising a source region and a drain region separated by a channel region and a gate positioned offset and spaced from the channel region. The biosensor also has one or more molecular probes coupled to at least one of the channel region and the offset gate, the one or more molecular probes configured to mate with at least one target. A method for detection of a target is also disclosed. One or more targets are immobilized as an electric field shunt between an offset gate and a channel region for one or more biosensors. A target measurement value is determined in proportion to a number of the one or more biosensors having the electric field shunt.
摘要翻译：生物传感器具有一个或多个场效应晶体管，每个场效应晶体管均包括由沟道区域分隔的源极区域和漏极区域以及与沟道区域偏置并间隔开的栅极。生物传感器还具有一个或多个分子探针，其耦合到通道区域和偏移栅极中的至少一个，所述一个或多个分子探针被配置为与至少一个靶材配合。还公开了一种用于检测靶的方法。一个或多个靶被固定为用于一个或多个生物传感器的偏移栅极和沟道区域之间的电场分流。与具有电场分流的一个或多个生物传感器的数量成比例地确定目标测量值。

37. 发明申请

US20130026450A1 NITRIDE-BASED HETEROJUCTION SEMICONDUCTOR DEVICE AND METHOD FOR THE SAME 有权
标题翻译：基于氮化物的异质半导体器件及其方法
公开(公告)号：US20130026450A1
公开(公告)日：2013-01-31
申请号：US13554455
申请日：2012-07-20
申请人： Jinhong Park , Kwangchoong Kim , Taehoon Jang
发明人： Jinhong Park , Kwangchoong Kim , Taehoon Jang
IPC分类号： H01L29/78 , H01L21/335
CPC分类号： H01L29/78 , H01L29/2003 , H01L29/205 , H01L29/24 , H01L29/41725 , H01L29/42316 , H01L29/66462 , H01L29/7786
摘要： Disclosed is a semiconductor device. More specifically, disclosed are a nitride-based heterojunction semiconductor device and a method for producing the same. The nitride-based heterojunction semiconductor device includes a nitride semiconductor buffer layer, a barrier layer disposed on the buffer layer, a cap layer discontinuously disposed on the barrier layer, a source electrode and a drain electrode that contact at least one of the barrier layer and the cap layer, and a gate electrode that Schottky-contacts at least one of the barrier layer and the cap layer and is disposed between the source electrode and the drain electrode.
摘要翻译：公开了一种半导体器件。更具体地，公开了一种氮化物基异质结半导体器件及其制造方法。氮化物基异质结半导体器件包括氮化物半导体缓冲层，设置在缓冲层上的阻挡层，不连续地设置在阻挡层上的覆盖层，源电极和漏电极，其与阻挡层和阻挡层中的至少一个接触所述盖层和与所述阻挡层和所述盖层中的至少一个肖特基接触并设置在所述源电极和所述漏电极之间的栅电极。

38. 发明授权

US08362525B2 Field effect device having a channel of nanofabric and methods of making same 有权
标题翻译：具有纳米通道的场效应器件及其制造方法
公开(公告)号：US08362525B2
公开(公告)日：2013-01-29
申请号：US11332529
申请日：2006-01-13
申请人： Claude L. Bertin , Mitchell Meinhold , Steven L. Konsek , Thomas Rueckes , Frank Guo
发明人： Claude L. Bertin , Mitchell Meinhold , Steven L. Konsek , Thomas Rueckes , Frank Guo
IPC分类号： H01L21/335 , H01L21/336 , H01L29/76
CPC分类号： B82Y10/00 , H01L21/823807 , H01L51/0048 , H01L51/0052 , H01L51/0508 , H01L51/0541
摘要： Field effect devices having channels of nanofabric and methods of making same. A nanotube field effect transistor is made to have a substrate, and a drain region and a source region in spaced relation relative to each other. A channel region is formed from a fabric of nanotubes, in which the nanotubes of the channel region are substantially all of the same semiconducting type of nanotubes. At least one gate is formed in proximity to the channel region so that the gate may be used to modulate the conductivity of the channel region so that a conductive path may be formed between the drain and source region. Forming a channel region includes forming a fabric of nanotubes in which the fabric has both semiconducting and metallic nanotubes and the fabric is processed to remove substantially all of the metallic nanotubes.
摘要翻译：具有纳米级通道的场效应器件及其制造方法。使纳米管场效应晶体管具有衬底，以及相对于彼此间隔开的漏极区域和源极区域。通道区域由纳米管的织物形成，其中沟道区的纳米管基本上都是相同的半导体类型的纳米管。在通道区域附近形成至少一个栅极，使得栅极可用于调制沟道区域的导电性，使得可以在漏极和源极区域之间形成导电路径。形成通道区域包括形成纳米管织物，其中织物具有半导体和金属纳米管，并且织物被处理以去除基本上所有的金属纳米管。

39. 发明授权

US08361844B2 Method for adjusting the height of a gate electrode in a semiconductor device 有权
标题翻译：用于调整半导体器件中的栅电极的高度的方法
公开(公告)号：US08361844B2
公开(公告)日：2013-01-29
申请号：US12754359
申请日：2010-04-05
申请人： Kai Frohberg , Heike Berthold , Katrin Reiche , Uwe Griebenow
发明人： Kai Frohberg , Heike Berthold , Katrin Reiche , Uwe Griebenow
IPC分类号： H01L21/335
CPC分类号： H01L21/28123 , H01L29/6653 , H01L29/66545 , H01L29/66575
摘要： By providing an implantation blocking material on the gate electrode structures of advanced semiconductor devices during high energy implantation processes, the required shielding effect with respect to the channel regions of the transistors may be accomplished. In a later manufacturing stage, the implantation blocking portion may be removed to reduce the gate electrode height to a desired level in order to enhance the process conditions during the deposition of an interlayer dielectric material, thereby significantly reducing the risk of creating irregularities, such as voids, in the interlayer dielectric material, even in densely packed device regions.
摘要翻译：通过在高能注入工艺期间在先进的半导体器件的栅电极结构上提供注入阻挡材料，可以实现相对于晶体管的沟道区所需的屏蔽效应。在稍后的制造阶段中，可以移除注入阻挡部分以将栅极电极的高度降低到期望的水平，以便在层间电介质材料的沉积期间增强工艺条件，从而显着降低产生不规则性的风险，例如在层间电介质材料中，甚至在密集装填区域也是空隙。

40. 发明申请

US20130015460A1 SEMICONDUCTOR STRUCTURE AND METHOD OF FORMING THE SAME 有权
标题翻译：半导体结构及其形成方法
公开(公告)号：US20130015460A1
公开(公告)日：2013-01-17
申请号：US13180268
申请日：2011-07-11
申请人： Po-Chih CHEN , Jiun-Lei Jerry YU , Fu-Wei YAO , Chun-Wei HSU , Fu-Chih YANG , Chun Lin TSAI
发明人： Po-Chih CHEN , Jiun-Lei Jerry YU , Fu-Wei YAO , Chun-Wei HSU , Fu-Chih YANG , Chun Lin TSAI
IPC分类号： H01L29/778 , H01L21/335 , H01L29/205
CPC分类号： H01L27/11578 , H01L21/28575 , H01L27/11565 , H01L29/0891 , H01L29/2003 , H01L29/42316 , H01L29/42376 , H01L29/452 , H01L29/66462 , H01L29/7787
摘要： An embodiment of the disclosure includes a semiconductor structure. The semiconductor structure includes a first III-V compound layer. A second III-V compound layer is disposed on the first III-V compound layer and different from the first III-V compound layer in composition. An interface is defined between the first III-V compound layer and the second III-V compound layer. A gate is disposed on the second III-V compound layer. A source feature and a drain feature are disposed on opposite side of the gate. Each of the source feature and the drain feature includes a corresponding metal feature at least partially embedded in the second III-V compound layer. A corresponding intermetallic compound underlies each metal feature. Each intermetallic compound contacts a carrier channel located at the interface.
摘要翻译：本公开的实施例包括半导体结构。半导体结构包括第一III-V族化合物层。第二III-V化合物层设置在第一III-V化合物层上，并且与组合物中的第一III-V化合物层不同。在第一III-V化合物层和第二III-V化合物层之间界定界面。栅极设置在第二III-V复合层上。源极特征和漏极特征设置在栅极的相对侧上。源特征和漏极特征中的每一个包括至少部分地嵌入第二III-V化合物层中的对应金属特征。相应的金属间化合物是每个金属特征的基础。每个金属间化合物接触位于界面处的载体通道。

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