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41. 发明授权

US11262964B2 Techniques for seamless transition between host display and remote display 有权
公开(公告)号：US11262964B2
公开(公告)日：2022-03-01
申请号：US16176913
申请日：2018-10-31
申请人： ATI Technologies ULC
发明人： Wei Liang , Jun Lei , Patrick Pak Kin Fok , Panagiotis Vagiakos , Aric Cyr , Min Zhang
IPC分类号： G06F3/14 , G09G5/12
摘要： Described herein are techniques for removing control of a display from an operating system. The disclosed techniques decouple operation of the physical display device from control of the operating system so that the display device may be powered down while not needed during streaming. The device driver for the graphics card, into which a display device cable is plugged, simulates operation of the display but allows the display to be powered down. Simulating the display involves properly responding to queries or commands from the operating system, and generating the signals that would be expected from the display device by the operating system. While simulated in this manner, whether the display device is actually powered down does not matter to the operation of an application being streamed, because the operating system still “believes” the display device is powered on. Thus application streaming is not interrupted by powering down the display device.

42. 发明申请

US20210405722A1 MULTI-DIE SYSTEM PERFORMANCE OPTIMIZATION 有权
公开(公告)号：US20210405722A1
公开(公告)日：2021-12-30
申请号：US17029852
申请日：2020-09-23
申请人： ADVANCED MICRO DEVICES, INC. , ATI TECHNOLOGIES ULC
发明人： Greg SADOWSKI , Sriram SUNDARAM , Stephen KUSHNIR , William C. BRANTLEY , Michael J. SCHULTE
IPC分类号： G06F1/28 , G05F1/625
摘要： A multi-die semiconductor package includes a first integrated circuit (IC) die having a first intrinsic performance level and a second IC die having a second intrinsic performance level different from the first intrinsic performance level. A power management controller distributes, based on a determined die performance differential between the first IC die and the second IC die, a level of power allocated to the semiconductor chip package between the first IC die and the second IC die. In this manner, the first IC die receives and operates at a first level of power resulting in performance exceeding its intrinsic performance level. The second IC die receives and operates at a second level of power resulting in performance below its intrinsic performance level, thereby reducing performance differentials between the IC dies.

43. 发明申请

US20210398505A1 FRAME-RATE BASED ILLUMINATION CONTROL AT DISPLAY DEVICE 有权
公开(公告)号：US20210398505A1
公开(公告)日：2021-12-23
申请号：US17464889
申请日：2021-09-02
申请人： ATI TECHNOLOGIES ULC
发明人： Ed CALLWAY , David GLEN
IPC分类号： G09G5/10 , G09G3/34 , G09G3/3208 , G06T15/50 , G09G3/20 , G06F3/01
摘要： A display system includes a rendering device and a display device. The rendering device is to render a sequence of frames for display at a frame rate and to set an illumination configuration to be applied by the display device during a frame period for each frame of the sequence of frames based on the frame rate. The illumination configuration controls at least one of an illumination level and a duration for an illumination strobe, and at least one of an illumination level for an illumination fill preceding the illumination strobe in the frame period and an illumination level for an illumination fill following the illumination strobe in the frame period. The display device is to receive a representation of the illumination configuration from the rendering device and apply the illumination configuration during a frame period for each frame of the sequence of frames to display the frame.

44. 发明申请

US20210377552A1 BANDWIDTH SAVING ARCHITECTURE FOR SCALABLE VIDEO CODING 有权
公开(公告)号：US20210377552A1
公开(公告)日：2021-12-02
申请号：US17403191
申请日：2021-08-16
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Lei Zhang , Ji Zhou , Zhen Chen , Min Yu
IPC分类号： H04N19/423 , H04N19/159 , H04N19/117 , H04N19/187 , H04N19/33
摘要： A system configured to perform scalable video encoding is provided. The system includes a memory; and a processing unit, wherein the processing unit is configured to: receive inter-layer data and a current picture, wherein the current picture has a base layer; upsample the inter-layer data to generate residual data and reconstruction data, wherein the inter-layer data includes a base mode flag; and encode the current picture to an enhanced layer using the upsampled inter-layer data based on a block type of the base layer and the base mode flag.

45. 发明授权

US11182186B2 Hang detection for virtualized accelerated processing device 有权
公开(公告)号：US11182186B2
公开(公告)日：2021-11-23
申请号：US15663499
申请日：2017-07-28
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Anthony Asaro , Yinan Jiang , Andy Sung , Ahmed M. Abdelkhalek , Xiaowei Wang , Sidney D. Fortes
IPC分类号： G06F9/46 , G06F9/455 , G06F9/48
摘要： A technique for recovering from a hang in a virtualized accelerated processing device (“APD”) is provided. In the virtualization scheme, different virtual machines are assigned different “time-slices” in which to use the APD. When a time-slice expires, the APD stops operations for a current VM and starts operations for another VM. To stop operations on the APD, a virtualization scheduler sends a request to idle the APD. The APD responds by completing work and idling. If one or more portions of the APD do not complete this idling process before a timeout expires, then a hang occurs. In response to the hang, the virtualization scheduler informs the hypervisor that a hang has occurred. The hypervisor performs a function level reset on the APD and informs the VM that the hang has occurred. The VM responds by stopping command issue to the APD and re-initializing the APD for the function.

46. 发明授权

US11153578B2 Gradient texturing compression codec 有权
公开(公告)号：US11153578B2
公开(公告)日：2021-10-19
申请号：US15965342
申请日：2018-04-27
申请人： ATI Technologies ULC
发明人： Navin Patel
IPC分类号： H04N19/186 , H04N19/176
摘要： Systems, apparatuses, and methods for performing computation-efficient encoding of video or image frames are disclosed. An encoder partitions a video or image frame into a plurality of sub-frame blocks. For each sub-frame block, the encoder selects a subset of the original pixel values based on one or more criteria. In a first mode, the encoder selects the corners of the sub-frame block. Then, the encoder generates encoding vectors to represent the pixels in between pairs of the selected subset of pixel values. The encoder includes the original pixel values of the selected subset in the encoded block that represents the original sub-frame block. The encoder also includes the encoding vectors in the encoded block, wherein the encoding vectors are calculated based on the color parameter differences between each pair of the selected subset of pixel values. The encoder also includes metadata specifying the encoding mode in the encoded block.

47. 发明申请

US20210275908A1 ADAPTING ENCODER RESOURCE ALLOCATION BASED ON SCENE ENGAGEMENT INFORMATION 有权
公开(公告)号：US20210275908A1
公开(公告)日：2021-09-09
申请号：US17193788
申请日：2021-03-05
申请人： Advanced Micro Devices, Inc. , ATI Technologies ULC
发明人： Ihab AMER , Thomas PERRY , Mehdi SAEEDI , Guennadi RIGUER , Gabor SINES , Yang LIU
IPC分类号： A63F13/25 , G06T7/90 , G06T7/11 , G06T7/215
摘要： An engagement analytics engine of a computing device analyzes one or more of scene representations, player inputs, or player meta information and generates corresponding engagement data indicative of a level of engagement corresponding to the represented scene. The engagement analytics engine generates encoding parameters based on the engagement data to cause scenes or regions within scenes to be encoded with a level of quality based on the indicated level of engagement. In some examples, the engagement analytics engine generates rendering parameters based on the engagement data to cause scenes to be rendered with a frame rate or quality parameters based on the indicated level of engagement. In some examples, the engagement analytics engine causes a load balancer to shift workloads associated with one or more scenes to higher or lower performance servers based on the engagement data.

48. 发明授权

US11108382B1 Oscillator calibration 有权
公开(公告)号：US11108382B1
公开(公告)日：2021-08-31
申请号：US17030452
申请日：2020-09-24
申请人： ATI Technologies ULC , Advanced Micro Devices, Inc.
发明人： Joyce Cheuk Wai Wong , Naeem Ibrahim Ally , Jonathan Hauke , Stephen Victor Kosonocky
IPC分类号： H03K3/03 , H03L7/06 , G06F1/08 , G06F1/10 , H03K5/159
摘要： An oscillator circuit includes a first oscillator, a second oscillator, and a calibration circuit to calibrate the first and second oscillators. The first oscillator is supplied with a first supply voltage, and the second oscillator is supplied with a second supply voltage. The calibration includes setting a frequency control of the second oscillator at a target frequency. Then, a voltage control of the second supply voltage is adjusted incrementally until a first control value is identified at which a second oscillator output frequency matches the target frequency. Then, a voltage control of the first supply voltage is set to the first control value. Then, the voltage control for the first supply voltage is adjusted incrementally until a second control value is identified at which a first oscillator output frequency is as close to the second oscillator output frequency as is achievable, but does not exceed it.

49. 发明授权

US11106039B2 Single-stream foveal display transport 有权
公开(公告)号：US11106039B2
公开(公告)日：2021-08-31
申请号：US16551069
申请日：2019-08-26
申请人： ATI Technologies ULC
发明人： Guennadi Riguer , Syed Athar Hussain
IPC分类号： G02B27/01 , G06F3/01 , G06F1/16 , G06F3/147
摘要： Systems, apparatuses, and methods for implementing a single-stream foveal display transport are disclosed. A system includes a transmitter sending an image over a display transport as a sequence of equi-sized rectangles to a receiver coupled to a display. The receiver then scales up the rectangles with different scale factors to cover display areas of different sizes. The pixel density within a rectangular region is uniform and scaling factors can take on integer or non-integer values. The rectilinear grid arrangement of the image results in simplified scaling operations for the display. In another scenario, the image is transmitted as a set of horizontal bands of equal size. Within each band, the same horizontal amount of transmitted pixels are redistributed across multiple rectangular regions of varied scales. The display stream includes embedded information and the horizontal and/or vertical distribution and scaling of rectangular regions, which can be adjusted for each transmitted image.

50. 发明授权

US11100889B2 Reducing 3D lookup table interpolation error while minimizing on-chip storage 有权
公开(公告)号：US11100889B2
公开(公告)日：2021-08-24
申请号：US16289260
申请日：2019-02-28
申请人： ATI Technologies ULC
发明人： Keith Lee , David I. J. Glen , Jie Zhou , Yuxin Chen
IPC分类号： G09G5/02 , G09G5/06
摘要： Systems, apparatuses, and methods for reducing three dimensional (3D) lookup table (LUT) interpolation error while minimizing on-chip storage are disclosed. A processor generates a plurality of mappings from a first gamut to a second gamut at locations interspersed throughout a 3D representation of the pixel component space. For example, in one implementation, the processor calculates mappings for 17×17×17 vertices within the 3D representation. Other implementations can include other numbers of vertices. Rather than increasing the number of vertices to reduce interpolation error, the processor calculates mappings for centroids of the sub-cubes defined by the vertices within the 3D representation of the first gamut. This results in a smaller increase to the LUT size as compared to increasing the number of vertices. The centroid mappings are used for performing tetrahedral interpolation to map source pixels in the first gamut into the second gamut with a reduced amount of interpolation error.

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