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1. 发明申请

US20230118950A1 COMPUTER PROCESSING UNIT INTRA-FRAME CLOCK AND VOLTAGE SCALING BASED ON GRAPHICS APPLICATION AWARENESS 有权
公开(公告)号：US20230118950A1
公开(公告)日：2023-04-20
申请号：US17963129
申请日：2022-10-10
申请人： QUALCOMM Incorporated
发明人： Edwin Jose , Ravi Jenkal , Donghyun Kim
IPC分类号： G06F1/08 , G06F9/48 , G06F9/38 , G06F1/3206
摘要： Computer processing unit intra-frame clock and voltage scaling based on graphics application awareness is disclosed. The computer processing unit includes a processor configured to execute a graphics application to generate a graphics image for output to a display. The computer processing unit includes a power management circuit configured to perform clock and voltage scaling (CVS) (i.e., frequency and/or voltage scaling) for the processor. The power management circuit is configured to identify a graphics application dispatched to be executed or being executed by the processor and to set the operating point for the processor based on the identified graphics application. This may allow the processor to operate at a more optimal operating point for performance of graphics and non-graphics applications as opposed to operating each application at a lower operating point due to a graphics application that is more current intensive.

2. 发明授权

US11630788B2 Clock generation for timing communications with ranks of memory devices 有权
公开(公告)号：US11630788B2
公开(公告)日：2023-04-18
申请号：US16921061
申请日：2020-07-06
申请人： Rambus Inc.
发明人： Jared L. Zerbe , Ian P. Shaeffer , John Eble
IPC分类号： G06F13/16 , G11C7/22 , G06F1/10 , G06F1/06 , G06F1/08 , G06F1/04 , G11C7/04 , H04L7/033
摘要： A memory controller includes a clock generator to generate a first clock signal and a timing circuit to generate a second clock signal from the first clock signal. The second clock signal times communications with any of a plurality of memory devices in respective ranks, including a first memory device in a first rank and a second memory device in a second rank. The timing circuit is configured to adjust a phase of the first clock signal, when the memory controller is communicating with the second memory device, based on calibration data associated with the second memory device and timing adjustment data associated with feedback from at least the first memory device.

3. 发明授权

US11630674B2 Smart overclocking method conducted in basic input/output system (BIOS) of computer device 有权
公开(公告)号：US11630674B2
公开(公告)日：2023-04-18
申请号：US17367154
申请日：2021-07-02
申请人： Tai-Sheng Han
发明人： Tai-Sheng Han
IPC分类号： G06F9/44 , G06F9/4401 , G06F11/30 , G06F11/07 , G06F1/08 , G06F1/14 , G06F1/20
摘要： The present invention provides a smart overclocking method for a computer device with a multi-core CPU and abasic input/output system (BIOS) where an overclocking database is stored therein, which comprises: booting the computer device, logging in the BIOS and performing an overclocking function; acquiring overclocking parameters from the overclocking database; conducting adjustment/settlement of the clock rate and the voltage of the multi-core CPU based on the overclocking parameters; conducting a Heavy Load Testing (HLT) on the multi-core CPU; reading out working results data of the multi-core CPU and determining whether any of them have exceeded limits. Hence, overclocking can be completed within 10 min. or less, without causing shut down of the computer device, and without causing working temperature or working voltage of multi-core CPU to be higher than 90° C. or 1500 mV during Heavy Load Testing (HLT).

4. 发明申请

US20230101038A1 DETERMINISTIC MIXED LATENCY CACHE 有权
公开(公告)号：US20230101038A1
公开(公告)日：2023-03-30
申请号：US17489741
申请日：2021-09-29
申请人： Advanced Micro Devices, Inc.
发明人： Patrick J. Shyvers
IPC分类号： G06F12/0891 , G06F12/02 , G06F3/06 , G06F1/08
摘要： A method and processing device for accessing data is provided. The processing device comprises a cache and a processor. The cache comprises a first data section having a first cache hit latency and a second data section having a second cache hit latency that is different from the first cache hit latency of the first data section. The processor is configured to request access to data in memory, the data corresponding to a memory address which includes an identifier that identifies the first data section of the cache. The processor is also configured to load the requested data, determined to be located in the first data section of the cache, according to the first cache hit latency of the first data section of the cache.

5. 发明申请

US20230099269A1 CLOCK CALIBRATION MODULE, HIGH-SPEED RECEIVER, AND ASSOCIATED CALIBRATION METHOD 有权
公开(公告)号：US20230099269A1
公开(公告)日：2023-03-30
申请号：US17565503
申请日：2021-12-30
申请人： FARADAY TECHNOLOGY CORPORATION
发明人： Vinod Kumar JAIN , Chi-Yeu CHAO
IPC分类号： G06F1/10 , G06F1/12 , G06F1/08
摘要： A clock calibration module, a high-speed receiver, and an associated calibration method are provided. The calibration method is applied to the high-speed receiver having the clock calibration module and a sampler. The sampler samples an equalized data signal with a sampler-input clock. The clock calibration module includes multiple clock generation circuits and a clock calibration circuit. Each of the clock generation circuits includes a phase interpolator, a duty cycle corrector, and a phase corrector. In a calibration mode, the phase interpolator interpolates a reference input clock and generates an interpolated clock accordingly. The duty cycle corrector generates a duty cycle corrected clock based on the interpolated clock. The phase corrector generates the sampler-input clock based on the duty cycle corrected clock. The phase interpolator is controlled by a phase interpolator calibration signal, and the phase corrector is controlled by a phase corrector calibration signal.

6. 发明申请

US20230096002A1 SEPARATE CLOCKING FOR COMPONENTS OF A GRAPHICS PROCESSING UNIT 有权
公开(公告)号：US20230096002A1
公开(公告)日：2023-03-30
申请号：US17890520
申请日：2022-08-18
申请人： ADVANCED MICRO DEVICES, INC.
发明人： Ranjith Kumar SAJJA , Sreekanth GODEY , Anirudh R. ACHARYA
IPC分类号： G06F1/08 , G06F9/50 , G06F11/34 , G06F1/12
摘要： Systems and methods related to controlling clock signals for clocking shader engines modules (SEs) and non-shader-engine modules (nSEs) of a graphics processing unit (GPU) are provided. One or more dividers receive a clock signal CLK and output a clock signal CLKA to the SEs and output a clock signal CLKB to the nSEs. The frequencies of CLKA and CLKB are independently selected based on sets of performance counter data monitored at the SEs and nSEs, respectively. The clock signal frequency for either the SEs or the nSEs is reduced when the corresponding sets of performance counter data indicates a comparatively lower processing workload for the SEs or for the nSEs.

7. 发明授权

US11615450B2 Checkins for services from a messenger chatbot 有权
公开(公告)号：US11615450B2
公开(公告)日：2023-03-28
申请号：US16420700
申请日：2019-05-23
申请人： SOHAM INC
发明人： Chaitanya Kapadia
IPC分类号： G06Q10/02 , G06Q30/0601 , H04L51/02 , G01C21/36 , G06F1/08 , G06F9/38 , G06Q10/1093 , G06Q50/00 , G06F9/54 , G10L15/22
摘要： A chatbot check-in platform includes a salon application associated with a messenger chatbot, wherein a user requests via the chatbot an appointment for a salon service. The platform includes a location service in communication with the salon application for finding a salon nearby a user; a salon services API in communication with the salon application for finding a requested salon service and time for appointment for the salon; and a database interface responding to a request for making an appointment with the salon. A method of using a chatbot check-in platform includes instructions, when executed by a processor, that cause the processor to execute actions including: receiving, by a first processor, a request received via an associated messenger chatbot for booking an appointment for a service provided by a salon, wherein the first processor is a processor of a device, the device includes machine readable memory accessible by the first processor; finding a salon and service, by the first processor in response the request; prompting, by the first processor, a booking for the salon and service via an associated chatbot; and upon receiving, by the first processor, a confirmation from the user via the chatbot, booking the salon and service.

8. 发明授权

US11615040B2 Structures and methods for adjusting a reference clock based on data transmission rate between PHY and MAC layers 有权
公开(公告)号：US11615040B2
公开(公告)日：2023-03-28
申请号：US17390428
申请日：2021-07-30
申请人： Texas Instruments Incorporated
发明人： Geet Govind Modi , Sumantra Seth , Subhashish Mukherjee
IPC分类号： G06F13/20 , G06F1/08
摘要： A system for data transmission includes a physical (PHY) layer which has a rate detection module which determines an adopted clock rate. The rate detection module provides a rate detection signal indicative of the adopted clock rate. The PHY layer includes a reference clock generator which has an input coupled to receive the rate detection signal and an output to provide a reference clock output. The PHY layer includes a PHY interface which has a first input coupled to receive the reference clock output, a data input and a data output. The PHY interface receives data from a MAC interface at the data input and transmits data to the MAC interface through the data output responsive to the reference clock output.

9. 发明授权

US11614768B2 Storage device and operating method thereof 有权
公开(公告)号：US11614768B2
公开(公告)日：2023-03-28
申请号：US17365252
申请日：2021-07-01
申请人： SK hynix Inc.
发明人： Kyeong Min Chae
IPC分类号： G06F1/08 , G06F1/24
摘要： A memory device including a clock generator generating a data processing clock signal based on an external clock signal, and an input/output circuit performing a data transmission/reception operation of transmitting/receiving data to/from an external device based on the data processing clock signal, wherein the clock generator comprises a warm-up operation controller generating a warm-up enable signal for recognizing a portion of a period of the external clock signal as a dummy signal, and resetting the warm-up enable signal when a pause period where a toggle of the external clock signal is temporarily stopped is detected.

10. 发明授权

US11611334B2 Method and circuit for monitoring and controlling duty margin of a signal 有权
公开(公告)号：US11611334B2
公开(公告)日：2023-03-21
申请号：US17504485
申请日：2021-10-18
申请人： MEDIATEK INC.
发明人： Shou-En Liu , Wen-Sung Chiang , Ming-Han Hsieh , Keng-Jui Chang , Lin-Chien Chen
IPC分类号： H03K3/017 , H03M13/25 , G06F1/08
摘要： A duty margin monitoring circuit, coupled to a functional circuit which generates a first output signal in response to a target signal, includes a modulation circuit, a replica circuit and an error detection circuit. The modulation circuit is arranged to receive the target signal and modulate the target signal to generate a modulated target signal. The replica circuit is arranged to receive the modulated target signal and generate a second output signal in response to the modulated target signal. The error detection circuit is coupled to the functional circuit and the replica circuit to receive the first output signal and the second output signal and arranged to generate an error detection result according to the first output signal and the second output signal.

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