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    • 50. 发明授权
    • Nand gate circuit, display back plate, display device and electronic device
    • 南门电路,显示背板,显示设备和电子设备
    • US09325315B2
    • 2016-04-26
    • US14420880
    • 2014-08-05
    • BOE TECHNOLOGY GROUP CO., LTD.
    • Zhongyuan WuDanna SongLiye Duan
    • H03K19/094H03K19/20H03K3/012H03K19/0185H03K19/0944
    • H03K19/018507H03K19/09441H03K19/09445H03K19/20
    • The NAND gate circuit includes at least two input transistors, at least two pull-up modules and at least two input control transistors. A first electrode of each input transistor is connected to a second level output end via the pull-up module. The input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate electrode of the input control transistor is at a second level. The at least two pull-up modules are configured to cut off the connection between the second level output end and the NAND gate output end when all the input signals are at the second level, and enable the connection therebetween when none of the input signals is at the second level.
    • NAND门电路包括至少两个输入晶体管,至少两个上拉模块和至少两个输入控制晶体管。 每个输入晶体管的第一电极通过上拉模块连接到第二电平输出端。 输入控制晶体管被配置为当连接到输入控制晶体管的栅电极的输入信号处于第一电平时,使连接到输入晶体管的第一电极的上拉模块的控制端的电位成为第一电平 第二级。 所述至少两个上拉模块被配置为当所有输入信号处于第二电平时切断第二电平输出端与NAND门输出端之间的连接,并且当没有输入信号为 在第二级。