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1. 发明授权

US11567621B2 Display panel, mobile terminal and method for controlling mobile terminal 有权
公开(公告)号：US11567621B2
公开(公告)日：2023-01-31
申请号：US16848562
申请日：2020-04-14
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Chungchun Lee , Li Zhou , Liye Duan , Feng Jiang , Xuan He , Long Wang
IPC分类号： G06F3/0481 , G06F3/0487 , G06F3/04883 , H04M1/02
摘要： Embodiments of the present disclosure provide a display panel, a mobile terminal and a method for controlling a mobile terminal which may allow a user to perform single hand operations on a large-size mobile terminal to improve the convenience of the mobile terminal. The display panel includes: a first substrate; a second substrate arranged opposite to the first substrate; and a single hand operation sensing unit arranged on the first substrate or the second substrate, which is configured to sense a single hand holding operation of a user and to trigger the display panel to demagnify an operation graphic interface displayed in full-screen and display the demagnified operation graphic interface in a predetermined single hand operation comfortable region positioned on the basis of a holding position in case that the single hand holding operation of the user is sensed.

2. 发明授权

US09842542B2 Display apparatus having a pixel structure for driving a plurality of organic light-emitting diodes 有权
公开(公告)号：US09842542B2
公开(公告)日：2017-12-12
申请号：US14894707
申请日：2015-04-17
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Liye Duan , Lirong Wang
IPC分类号： G09G3/32 , G09G3/3258 , G09G3/3233
CPC分类号： G09G3/3258 , G09G3/32 , G09G3/3233 , G09G2300/0426 , G09G2300/0465 , G09G2300/0804 , G09G2300/0809 , G09G2300/0814 , G09G2300/0842 , G09G2300/0861
摘要： There are provided a pixel structure, a display panel and a display apparatus. The pixel structure comprises a pixel circuit (11), a switch circuit (12) and n organic light-emitting diodes (13) sharing the pixel circuit (11), where n is greater than or equal to 2. Respective organic light-emitting diodes (13) sharing the pixel circuit (11) are located in a same column of the display panel, and emit lights of a same color when emitting light. The switch circuit (12) is configured to control any two organic light-emitting diodes (13) sharing the pixel circuit (11) to emit light at different periods of time. The pixel circuit (11) is configured to drive of the respective organic light-emitting diodes sharing the pixel circuit (11) to emit light according to a received data signal. The pixel structure is used to solve the problem of the complexity of the back board.

3. 发明授权

US09799271B2 Gate driver, display apparatus and gate driving method of outputting a multi-pulse waveform 有权
公开(公告)号：US09799271B2
公开(公告)日：2017-10-24
申请号：US14770364
申请日：2015-01-30
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Lirong Wang , Liye Duan , Zhongyuan Wu
IPC分类号： G09G3/36 , G09G3/3266 , G09G3/3258 , G11C19/28
CPC分类号： G09G3/3266 , G09G3/3258 , G09G2300/0814 , G09G2310/0218 , G09G2310/0286 , G09G2310/08 , G09G2320/0233 , G09G2330/023 , G11C19/28
摘要： The present disclosure discloses a gate driver, a display apparatus and a gate driving method, to achieve a function of outputting a multi-pulse waveform by the gate driver. The gate driver according to the present disclosure comprises multiple groups of driving units, each group of driving units comprising N driving units each of which comprises a shift register and a logic circuit, wherein N is an integer larger than 1, and an output of a shift register is connected to a logic circuit in each driving unit. The shift registers multiplex multiple clock signals with different timings. Each of the shift registers outputs an output signal to a corresponding logic circuit. A part of a clock signal is selected by the logic circuit for output. In this way, a function of outputting a multi-pulse waveform by the gate driver is achieved, which prepares for a shift register having a function of threshold voltage compensation, to make a shift register capable of multi-row scanning become feasible on a display panel.

4. 发明授权

US09755624B2 Ramp signal generating circuit and signal generator, array substrate and display apparatus 有权
公开(公告)号：US09755624B2
公开(公告)日：2017-09-05
申请号：US14429516
申请日：2014-04-28
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Liye Duan , Lirong Wang , Zhongyuan Wu
IPC分类号： G09G5/20 , H03K4/08 , H03K4/06 , G09G3/20
CPC分类号： H03K4/06 , G09G3/20 , G09G5/20 , G09G2300/0408 , G09G2310/0259 , G09G2310/066 , H03K4/08
摘要： A ramp signal generating circuit and ramp signal generator, an array substrate and a display apparatus. The ramp signal generating circuit comprises a first shift register (11), a second shift register (12), a voltage decreasing unit (13) and a sampling unit (14); the voltage decreasing unit (13) is connected to a first power supply input terminal, a second power supply input terminal and a ground terminal and is configured to continuously decrease a voltage inputted from the first power supply input terminal and a voltage inputted from the second power supply input terminal stage by stage; the first shift register (11) is connected to the voltage decreasing unit (13) and is configured to control the voltage decreasing unit (13) to output voltages which are decreased continuously stage by stage; the sampling unit (14) has an output terminal and is connected to the voltage decreasing unit (13); the second shift register (12) is connected to the sampling unit (14) and is configured to control the sampling unit (14) to sample and output the voltages which are decreased continuously stage by stage and outputted by the voltage decreasing unit (13). Such ramp signal generating circuit is capable of reducing area of the ramp signal generating circuit and improving linearity of ramp signal.

5. 发明授权

US09681074B2 Pixel circuit including compensation unit, driving method thereof and detector 有权
公开(公告)号：US09681074B2
公开(公告)日：2017-06-13
申请号：US15103979
申请日：2015-10-20
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Liye Duan , Chung-Chun Lee , Feng Jiang , Li Zhou , Long Wang , Chieh Hsing Chung
IPC分类号： H04N5/235 , H04N5/357 , G01T1/24 , H04N5/66 , H04N5/3745 , H04N5/32
CPC分类号： H04N5/357 , G01T1/247 , G09G3/00 , H04N5/32 , H04N5/365 , H04N5/3745 , H04N5/37457 , H04N5/66
摘要： A pixel circuit is provided. The pixel circuit includes a photoelectric converter unit, an amplifier unit, a reset unit, a compensation unit, a charging unit, and a readout unit, wherein the photoelectric converter unit is connected to a first voltage terminal and the amplifier unit, and is configured to convert an optical signal into an electric signal, wherein the amplifier unit is connected to the photoelectric converter unit, the charging unit, and the readout unit, and is configured to amplify an output signal from the photoelectric converter unit, and wherein the reset unit is connected to a reset terminal, the first voltage terminal, and the amplifier unit, and is configured to reset the amplifier unit based on an input signal from the reset terminal and an input signal from the first voltage terminal.

6. 发明授权

US09325315B2 Nand gate circuit, display back plate, display device and electronic device 有权
标题翻译：南门电路，显示背板，显示设备和电子设备
公开(公告)号：US09325315B2
公开(公告)日：2016-04-26
申请号：US14420880
申请日：2014-08-05
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Zhongyuan Wu , Danna Song , Liye Duan
IPC分类号： H03K19/094 , H03K19/20 , H03K3/012 , H03K19/0185 , H03K19/0944
CPC分类号： H03K19/018507 , H03K19/09441 , H03K19/09445 , H03K19/20
摘要： The NAND gate circuit includes at least two input transistors, at least two pull-up modules and at least two input control transistors. A first electrode of each input transistor is connected to a second level output end via the pull-up module. The input control transistor is configured to enable a potential of the control end of the pull-up module connected to the first electrode of the input transistor to be the first level when the input signal connected to the gate electrode of the input control transistor is at a second level. The at least two pull-up modules are configured to cut off the connection between the second level output end and the NAND gate output end when all the input signals are at the second level, and enable the connection therebetween when none of the input signals is at the second level.
摘要翻译： NAND门电路包括至少两个输入晶体管，至少两个上拉模块和至少两个输入控制晶体管。每个输入晶体管的第一电极通过上拉模块连接到第二电平输出端。输入控制晶体管被配置为当连接到输入控制晶体管的栅电极的输入信号处于第一电平时，使连接到输入晶体管的第一电极的上拉模块的控制端的电位成为第一电平第二级。所述至少两个上拉模块被配置为当所有输入信号处于第二电平时切断第二电平输出端与NAND门输出端之间的连接，并且当没有输入信号为在第二级。

7. 发明授权

US09257084B2 Shift register unit and gate driver circuit 有权
标题翻译：移位寄存器单元和栅极驱动电路
公开(公告)号：US09257084B2
公开(公告)日：2016-02-09
申请号：US14366534
申请日：2013-12-17
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Kun Cao , Zhongyuan Wu , Liye Duan
IPC分类号： G09G3/36 , G11C19/28
CPC分类号： G09G3/3648 , G09G3/3677 , G09G2310/0286 , G09G2310/067 , G09G2320/043 , G11C19/28
摘要： Provided are a shift register unit and a gate driver circuit, which are configured to suppress output errors caused by the drifts in the threshold voltages and the interval existed in the operation of pulling the output terminal, and thus to enhance stability of the shift register unit. The shift register unit comprises: an input module, a first output module, a pull-down driving module, a pull-down module and a first output discharging unit. The pull-down driving module is connected to the first clock signal input terminal and the second clock signal input terminal, and configured to provide the first clock signal to a first pull-down node in response to the first clock signal, provide the second clock signal to a second pull-down node in response to the second clock signal, provide a first low voltage signal to the first pull-down node and the second pull-down node in response to the voltage signal at the pull-up node, provide the first low voltage signal to the second pull-down node in response to a voltage signal at the first pull-down node, and provide the first low voltage signal to the first pull-down node in response to a voltage signal at the second pull-down node.
摘要翻译：提供了一种移位寄存器单元和栅极驱动器电路，其被配置为抑制由阈值电压中的漂移和拉动输出端子的操作中存在的间隔引起的输出误差，从而增强移位寄存器单元的稳定性。移位寄存器单元包括：输入模块，第一输出模块，下拉驱动模块，下拉模块和第一输出放电单元。下拉驱动模块连接到第一时钟信号输入端和第二时钟信号输入端，并被配置为响应于第一时钟信号将第一时钟信号提供给第一下拉节点，提供第二时钟响应于第二时钟信号向第二下拉节点发送信号，响应于上拉节点处的电压信号向第一下拉节点和第二下拉节点提供第一低电压信号，提供所述第一低电压信号响应于所述第一下拉节点处的电压信号而被提供给所述第二下拉节点，并且响应于所述第二拉动期间的电压信号将所述第一低电压信号提供给所述第一下拉节点下降节点。

8. 发明授权

US09099417B2 Pixel circuit, driving method thereof and display device 有权
标题翻译：像素电路，其驱动方法和显示装置
公开(公告)号：US09099417B2
公开(公告)日：2015-08-04
申请号：US14236283
申请日：2013-08-12
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Jingwen Yin , Zhongyuan Wu , Liye Duan
IPC分类号： H01L27/32 , G09G3/32
CPC分类号： H01L27/3265 , G09G3/325 , G09G2310/0251 , G09G2310/0262 , G09G2310/067 , G09G2320/045
摘要： The present invention relates to the field of display technology, and provides a pixel circuit, a driving method thereof, and a display device, so as to compensate for the TFT threshold voltage drift, thereby to improve the brightness non-uniformity of the display device and prolong the service life thereof. The pixel circuit comprises a first transistor, a second transistor, a third transistor, a fourth transistor, a fifth transistor, a first storage capacitor, a second storage capacitor, and a light-emitting element. The present invention is adapted to manufacture a display panel.
摘要翻译：本发明涉及显示技术领域，并提供像素电路及其驱动方法和显示装置，以补偿TFT阈值电压漂移，从而提高显示装置的亮度不均匀性并延长其使用寿命。像素电路包括第一晶体管，第二晶体管，第三晶体管，第四晶体管，第五晶体管，第一存储电容器，第二存储电容器和发光元件。本发明适用于制造显示面板。

9. 发明申请

US20150207492A1 RAMP SIGNAL GENERATING CIRCUIT AND SIGNAL GENERATOR, ARRAY SUBSTRATE AND DISPLAY APPARATUS 有权
标题翻译： RAMP信号发生电路和信号发生器，阵列基板和显示设备
公开(公告)号：US20150207492A1
公开(公告)日：2015-07-23
申请号：US14416821
申请日：2014-04-28
申请人： BOE TECHNOLOGY GROUP CO., LTD.
发明人： Liye Duan , Lirong Wang , Zhongyuan Wu
IPC分类号： H03K3/012 , H03K5/01
CPC分类号： H03K4/48 , G09G3/20 , G09G2300/0408 , G09G2310/0259 , G09G2310/0264 , G09G2310/066 , H03K4/026 , H03K4/90
摘要： A ramp signal generating circuit and ramp signal generator, an array substrate and a display apparatus. The ramp signal generating circuit comprises a first shift register (11), a second shift register possessing a bidirectional scanning function (12), a voltage decreasing unit (13) and a sampling unit (14); the voltage decreasing unit (13) is connected to a power supply input terminal and a ground terminal and is configured to continuously decrease a voltage inputted from the power supply input terminal stage by stage; the first shift register (11) is connected to the voltage decreasing unit (13) and is configured to control the voltage decreasing unit (13) to output voltages which are decreased continuously stage by stage; the sampling unit (14) has an output terminal and is connected to the voltage decreasing unit (13); the second shift register (12) is connected to the sampling unit (14) and is configured to control, through bidirectional scanning, the sampling unit (13) to sample and output the voltages which are decreased continuously stage by stage by the voltage decreasing unit (13). Such ramp signal generating circuit is capable of reducing area of the ramp signal generating circuit and improving linearity of ramp signal.
摘要翻译：斜坡信号发生电路和斜坡信号发生器，阵列基板和显示装置。斜坡信号发生电路包括第一移位寄存器（11），具有双向扫描功能的第二移位寄存器（12），降压单元（13）和采样单元（14）; 电压降低单元（13）连接到电源输入端子和接地端子，并且被配置为逐级地连续地降低从电源输入端子输入的电压; 第一移位寄存器（11）连接到降压单元（13），并且被配置为控制电压降低单元（13）输出逐级逐渐减小的电压; 采样单元（14）具有输出端子，并连接到降压单元（13）; 第二移位寄存器（12）连接到采样单元（14），并且被配置为通过双向扫描来控制采样单元（13）对由电压降低单元逐级逐级地降低的电压进行采样和输出（13）。这种斜坡信号发生电路能够减小斜坡信号发生电路的面积并提高斜坡信号的线性度。

10. 发明申请

US20140192444A1 Electro-Static Discharge Protection Circuit, Array Substrate And Display Apparatus 有权
标题翻译：静电放电保护电路，阵列基板和显示装置
公开(公告)号：US20140192444A1
公开(公告)日：2014-07-10
申请号：US13995134
申请日：2012-11-21
申请人： BOE Technology Group Co., Ltd.
发明人： Zhongyuan Wu , Liye Duan
IPC分类号： H02H9/04
CPC分类号： H02H9/04 , G02F1/136204 , G09G3/20 , G09G2330/04 , H01L27/0296 , H02H3/046
摘要： Provided is an electro-static discharge protection circuit, an array substrate and a display apparatus, being capable of reducing power consumption while improving reliability of the display apparatus. The electro-static discharging protection circuit comprises: a first thin film transistor (T1), having a drain connected to a high level output terminal (VGH); a second thin film transistor (T2), having a source connected to a source of the first thin film transistor (T1) as a discharging terminal (O), a drain connected to the high level output terminal (VGH) and a gate connected to a low level output terminal (VGL); a third thin film transistor (T3), having a source and a gate connected to the low level output terminal (VGL) and a drain connected to the gate of the first thin film transistor (T1); and a voltage difference maintaining unit connected between the gate of the first thin film transistor (T1) and the discharging terminal (O), wherein the voltage difference maintaining unit is used to make the voltage difference between the gate of the first thin film transistor (T1) and the discharging terminal (O) maintain unchanged, the discharging terminal (O) being used for connecting gate lines or data lines.
摘要翻译：提供一种静电放电保护电路，阵列基板和显示装置，能够在提高显示装置的可靠性的同时降低功耗。静电放电保护电路包括：第一薄膜晶体管（T1），其漏极连接到高电平输出端子（VGH）; 第二薄膜晶体管（T2），其源极连接到作为放电端子（O）的第一薄膜晶体管（T1）的源极，漏极连接到高电平输出端子（VGH），栅极连接到低电平输出端子（VGL）; 具有连接到低电平输出端子（VGL）的源极和栅极的第三薄膜晶体管（T3）和连接到第一薄膜晶体管（T1）的栅极的漏极; 以及连接在第一薄膜晶体管（T1）的栅极和放电端子（O）之间的电压差保持单元，其中，电压差维持单元用于使第一薄膜晶体管（I）的栅极之间的电压差 T1）和放电端子（O）保持不变，放电端子（O）用于连接栅线或数据线。

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