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41. 发明授权

US09558152B2 Synchronization method, multi-core processor system, and synchronization system 有权
标题翻译：同步方法，多核处理器系统和同步系统
公开(公告)号：US09558152B2
公开(公告)日：2017-01-31
申请号：US14026469
申请日：2013-09-13
申请人： FUJITSU LIMITED
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F9/46 , G06F15/78 , G06F9/52 , G06F9/54 , G06F15/167 , G06F9/45 , G06F9/38 , G06F9/30
CPC分类号： G06F15/7839 , G06F8/458 , G06F9/30087 , G06F9/3834 , G06F9/3838 , G06F9/3842 , G06F9/3885 , G06F9/467 , G06F9/52 , G06F9/544 , G06F15/167 , G06F2212/507
摘要： A synchronization method is executed by a multi-core processor system. The synchronization method includes registering based on a synchronous command issued from a first CPU, CPUs to be synchronized and a count of the CPUs into a specific table; counting by each of the CPUs and based on a synchronous signal from the first CPU, an arrival count for a synchronous point, and creating by each of the CPUs, a second shared memory area that is a duplication of a first shared memory area accessed by processes executed by the CPUs; and comparing the first shared memory area and the second shared memory area when the arrival count becomes equal to the count of the CPUs, and based on a result of the comparison, judging the processes executed by the CPUs.
摘要翻译：同步方法由多核处理器系统执行。同步方法包括基于从第一CPU发出的同步命令，要同步的CPU和CPU的计数到特定表中进行注册; 由每个CPU进行计数，并且基于来自第一CPU的同步信号，同步点的到达计数以及由每个CPU创建作为第一共享存储器区域的复制的第二共享存储区域由CPU执行的进程; 以及当到达计数等于CPU的计数时，比较第一共享存储区域和第二共享存储区域，并且基于比较结果，判断由CPU执行的处理。

42. 发明授权

US09459870B2 Data processor 有权
标题翻译：数据处理器
公开(公告)号：US09459870B2
公开(公告)日：2016-10-04
申请号：US14499334
申请日：2014-09-29
申请人： FUJITSU LIMITED
发明人： Toshiya Otomo , Koichiro Yamashita , Takahisa Suzuki , Hiromasa Yamauchi , Koji Kurihara , Yuta Teranishi
IPC分类号： G06F9/30 , G06F9/34 , G06F15/167
CPC分类号： G06F9/30043 , G06F9/30 , G06F9/30036 , G06F9/34 , G06F15/167
摘要： A data processor includes: a plurality of controllers that process data; a program memory that stores a standby instruction and a data processing instruction at a plurality of addresses respectively; and a queue that stores different execution start addresses for the plurality of controllers, wherein after the plurality of controllers sequentially access the queue, the plurality of controllers acquire the different execution start addresses from the queue in an order of the sequential access, start execution of instructions from the acquired different execution start addresses in the program memory, and execute the data processing instruction and execute the standby instruction the number of times different for each of the controllers.
摘要翻译：数据处理器包括：处理数据的多个控制器; 程序存储器，分别在多个地址上存储备用指令和数据处理指令; 以及存储多个控制器的不同执行开始地址的队列，其中，在所述多个控制器顺序访问所述队列之后，所述多个控制器以所述顺序访问的顺序从所述队列获取不同的执行开始地址，开始执行来自程序存储器中获取的不同执行开始地址的指令，并且执行数据处理指令并且执行备用指令，以使每个控制器不同的次数。

43. 发明授权

US09448931B2 Endian conversion method and system 有权
标题翻译： Endian转换方法和系统
公开(公告)号：US09448931B2
公开(公告)日：2016-09-20
申请号：US14029425
申请日：2013-09-17
申请人： FUJITSU LIMITED
发明人： Akihito Kataoka , Koichiro Yamashita , Naoki Odate , Takahisa Suzuki , Hiromasa Yamauchi , Koji Kurihara , Toshiya Otomo
IPC分类号： G06F13/10 , G06F12/06 , G06F7/76
CPC分类号： G06F12/06 , G06F7/768 , G06F2213/0038
摘要： An endian conversion method is executed by a CPU, and includes executing a program that includes endian conversion setting; and performing, when accessing an address of a main memory indicated in the endian conversion setting, endian conversion of data specified by the address of the main memory.
摘要翻译：一个字节序转换方法由CPU执行，并且包括执行一个包括字节序转换设置的程序; 并且当访问在所述末端转换设置中指示的主存储器的地址时，执行由所述主存储器的地址指定的数据的末端转换。

44. 发明授权

US09430388B2 Scheduler, multi-core processor system, and scheduling method 有权
公开(公告)号：US09430388B2
公开(公告)日：2016-08-30
申请号：US14601978
申请日：2015-01-21
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F12/08 , G06F9/48 , G06F9/54 , B29C49/06 , B29C49/42 , B29D22/00 , B29C49/18 , B29C49/64
CPC分类号： G06F12/0811 , B29C49/062 , B29C49/18 , B29C49/4215 , B29C49/6427 , B29D22/003 , G06F9/544 , G06F12/0875 , G06F12/0888 , G06F2212/283
摘要： A scheduler that causes a given core in a multi-core processor to determine if a priority level of a process that is to be executed by a core of the multi-core processor is greater than or equal to a threshold; save to a cache memory of each core that executes a process having a priority level greater than or equal to the threshold, data that is accessed by the process upon execution; save to a memory area different from the cache memory and to which access is relatively slower, data that is accessed by a process having a priority level not greater than or equal to the threshold; and save the data saved in the memory area, to a cache memory of a requesting core, when the requesting core issues an access request for the data saved in the memory area.

45. 发明授权

US09367459B2 Scheduling method and multi-core processor system 有权
标题翻译：调度方法和多核处理器系统
公开(公告)号：US09367459B2
公开(公告)日：2016-06-14
申请号：US13934951
申请日：2013-07-03
申请人： FUJITSU LIMITED
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara
IPC分类号： G06F9/38 , G06F12/08 , G06F9/48 , G06F3/06 , G06F12/02 , G06F9/50
CPC分类号： G06F12/0815 , G06F3/065 , G06F9/3851 , G06F9/4843 , G06F9/5016 , G06F12/0284 , Y02D10/13 , Y02D10/22
摘要： A scheduling method of a scheduler that manages threads is executed by a computer. The scheduling method includes selecting a CPU of relatively less load, when a second thread is generated from a first thread to be processed; determining whether the second thread operates exclusively from the first thread; copying a first storage area assessed by the first thread onto a second storage area managed by the CPU, when the second thread operates exclusively; calculating based on an address of the second storage area and a predetermined value, an offset for a second address for the second thread to access the first storage area; and notifying the CPU of the offset for the second address to convert a first address to a third address for accessing the second storage area.
摘要翻译：管理线程的调度器的调度方法由计算机执行。调度方法包括当从要处理的第一线程生成第二线程时，选择相对较小负载的CPU; 确定所述第二线程是否仅从所述第一线程操作; 当第二线程专门操作时，将由第一线程评估的第一存储区域复制到由CPU管理的第二存储区域上; 基于第二存储区域的地址和预定值计算第二线程的访问第一存储区域的第二地址的偏移量; 并向CPU通知第二地址的偏移量，以将第一地址转换为用于访问第二存储区域的第三地址。

46. 发明申请

US20160112280A1 DATA NETWORK MANAGEMENT SYSTEM, DATA NETWORK MANAGEMENT APPARATUS, DATA PROCESSING APPARATUS, AND DATA NETWORK MANAGEMENT METHOD 审中-公开
标题翻译：数据网络管理系统，数据网络管理设备，数据处理设备和数据网络管理方法
公开(公告)号：US20160112280A1
公开(公告)日：2016-04-21
申请号：US14979417
申请日：2015-12-27
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Toshiya Otomo
IPC分类号： H04L12/24
CPC分类号： H04L41/32 , H04L41/085 , H04L41/28 , H04W24/02
摘要： A data network management system includes a data network management apparatus; and plural data processing apparatuses installed in an installation area and configured to transmit data to the data network management apparatus. The plural data processing apparatuses transmit identification information thereof together with the processed data to the data network management apparatus. The data network management apparatus determines based on identification information of data processing apparatuses that have completed a given authentication test among the plural data processing apparatuses and the identification information obtained from the plural data processing apparatuses installed in the installation area, a first data processing apparatus from which the data is to be obtained among the plural data processing apparatuses.
摘要翻译：数据网络管理系统包括数据网络管理装置; 以及多个数据处理装置，安装在安装区域并被配置为向数据网络管理装置发送数据。多个数据处理装置将其处理后的数据的识别信息与数据网络管理装置进行通信。数据网络管理装置根据在多个数据处理装置中完成了给定认证测试的数据处理装置的识别信息和从安装在安装区域的多个数据处理装置获得的识别信息，确定第一数据处理装置，在多个数据处理装置中获得数据。

47. 发明申请

US20160073355A1 COMMUNICATIONS NODE, SYSTEM, COMMUNICATIONS METHOD, AND COMPUTER PRODUCT 审中-公开
标题翻译：通信节点，系统，通信方法和计算机产品
公开(公告)号：US20160073355A1
公开(公告)日：2016-03-10
申请号：US14943226
申请日：2015-11-17
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Toshiya Otomo , Miyoshi Saito
IPC分类号： H04W52/24 , H04W24/10 , H04W48/16 , H04W72/08
CPC分类号： H04W52/245 , H04B17/27 , H04W24/10 , H04W40/12 , H04W48/16 , H04W52/283 , H04W52/383 , H04W52/46 , H04W72/087 , H04W84/18 , Y02D70/00 , Y02D70/34
摘要： A communications node includes a first transmitting circuit configured to transmit to plural communications nodes, a confirmation signal for confirming whether response is possible; a receiving circuit configured to receive from first communications nodes capable of responding among the plural communications nodes, a response signal for the transmitted confirmation signal; a selecting circuit configured to select from among the first communications nodes and based on reception strength of the received response signal, a second communications node to which execution of data processing is requested by the communications node; a strength calculating circuit configured to calculate based on the reception strength of the response signal from the selected second communications node, a transmission strength to the second communications node; and a second transmitting circuit configured to transmit to the second communications node and based on the calculated transmission strength, a request signal requesting execution of the data processing.
摘要翻译：通信节点包括：第一发送电路，被配置为向多个通信节点发送用于确认响应是否可能的确认信号; 接收电路，被配置为从所述多个通信节点中能够响应的第一通信节点接收用于所发送的确认信号的响应信号; 选择电路，被配置为从所述第一通信节点中选择并且基于所接收的响应信号的接收强度，所述通信节点请求执行数据处理的第二通信节点; 强度计算电路，被配置为基于来自所选择的第二通信节点的响应信号的接收强度计算到第二通信节点的传输强度; 以及第二发送电路，被配置为向所述第二通信节点发送基于所计算的发送强度的请求信号，所述请求信号请求执行所述数据处理。

48. 发明授权

US09274827B2 Data processing apparatus, transmitting apparatus, transmission control method, scheduling method, and computer product 有权
标题翻译：数据处理装置，发送装置，传输控制方法，调度方法和计算机产品
公开(公告)号：US09274827B2
公开(公告)日：2016-03-01
申请号：US14316285
申请日：2014-06-26
申请人： FUJITSU LIMITED
发明人： Hiromasa Yamauchi , Koichiro Yamashita , Takahisa Suzuki , Koji Kurihara , Toshiya Otomo , Yuta Teranishi
IPC分类号： G06F3/00 , G06F9/44 , G06F9/46 , G06F9/48
CPC分类号： G06F9/46 , G06F9/4812 , Y02D10/24
摘要： A data processing apparatus includes a processor configured to receive an interrupt request that is a trigger for execution of an interrupt process executed by the processor; store the received interrupt request to a recording area; calculate based on a time when the interrupt request is received and particular time information read from the recording area, a predicted time when a subsequent interrupt request is to be received; detect a thread to be executed by the processor, among executable threads of the processor; judge based on the calculated predicted time and a current time, whether there is a possibility of the interrupt process being executed while the detected thread is under execution; decide based on a judgment result, whether to execute the detected thread on the processor; and execute the detected thread on the processor, based on a decision result.
摘要翻译：一种数据处理装置，包括：处理器，被配置为接收作为用于执行由处理器执行的中断处理的触发的中断请求; 将接收到的中断请求存储到记录区域; 基于接收到中断请求的时间和从记录区读取的特定时间信息，接收到后续中断请求的预测时间计算; 在处理器的可执行线程中检测要由处理器执行的线程; 基于所计算的预测时间和当前时间来判断在检测到的线程正在执行时是否存在执行中断处理的可能性; 根据判断结果决定是否在处理器上执行检测到的线程; 并且基于判定结果在处理器上执行检测到的线程。

49. 发明授权

US09170862B2 Converting apparatus, conversion method, and information processing system 有权
标题翻译：转换装置，转换方法和信息处理系统
公开(公告)号：US09170862B2
公开(公告)日：2015-10-27
申请号：US14669638
申请日：2015-03-26
申请人： FUJITSU LIMITED
发明人： Koichiro Yamashita , Hiromasa Yamauchi , Takahisa Suzuki , Koji Kurihara , Toshiya Otomo
IPC分类号： G06F13/00 , G06F9/54 , G06F12/02 , G06F9/44
CPC分类号： G06F9/542 , G06F1/3212 , G06F1/3287 , G06F9/4401 , G06F9/4405 , G06F9/4812 , G06F12/0292 , G06F2212/1016 , G06F2212/65 , Y02D10/171 , Y02D10/174
摘要： A converting apparatus includes a storage configured to store correspondence information that indicates correspondence relations between logical addresses accessed by a processor for booting and physical addresses converted from the logical addresses, the correspondence information being correlated with each type of an event booting the processor; and an address converter configured to select correspondence information related to the type of the event, specify a physical address converted from the logical address accessed by the processor in case of the processor accessing a logical address in response to the event, and control the processor to get a program stored in the storage, the program indicated by the specified physical address.
摘要翻译： A转换装置包括：存储器，被配置为存储指示由处理器访问的用于引导的逻辑地址与从逻辑地址转换的物理地址之间的对应关系的对应信息;对应信息与引导处理器的每种类型的事件相关; 以及地址转换器，其被配置为选择与所述事件的类型相关的对应信息，在处理器响应于所述事件访问逻辑地址的情况下指定从所述处理器访问的逻辑地址转换的物理地址，并且将所述处理器控制为获得存储在程序中的程序，程序由指定的物理地址指定。

50. 发明授权

US09037808B2 Restoring data using parity when suspending a core of a multicore processor 有权
标题翻译：在挂起多核处理器核心时，使用奇偶校验恢复数据
公开(公告)号：US09037808B2
公开(公告)日：2015-05-19
申请号：US13730514
申请日：2012-12-28
申请人： FUJITSU LIMITED
发明人： Takahisa Suzuki , Koichiro Yamashita , Hiromasa Yamauchi , Koji Kurihara
IPC分类号： G06F12/08 , G06F1/32 , G06F1/30 , G06F11/10 , G06F12/06
CPC分类号： G06F1/30 , G06F11/1004 , G06F11/1076 , G06F12/0646 , G06F12/0804 , G06F2211/1059 , G06F2212/1028 , G06F2212/254
摘要： A computer-readable recording medium stores a program that causes a computer capable of accessing a multicore processor equipped with volatile memories and a plurality of cores accessing the volatile memories, to execute a data restoration process. The data restoration process includes detecting a suspend instruction to any one of the cores in the multicore processor; and restoring, when the suspend instruction is detected, data stored in a volatile memory accessed by a core receiving the suspend instruction, the data being restored in a shared memory accessed by the cores in operation and based on parity data stored in the volatile memories accessed by the cores in operation other than the core receiving the suspend instruction.
摘要翻译：计算机可读记录介质存储使能够访问配备有易失性存储器的多核处理器和访问易失性存储器的多个核的计算机执行数据恢复处理的程序。所述数据恢复处理包括检测对所述多核处理器中的任一核的挂起指令; 并且当检测到所述暂停指令时，恢复存储在由接收到所述挂起指令的核心访问的易失性存储器中的数据，所述数据被恢复在由所述核操作的存储器访问的共享存储器中，并且基于存储在所访问的所述易失性存储器中的奇偶校验数据由核心在核心以外的核心接收暂停指令。

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