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41. 外观设计

USD547215S1 Laser level 有权
标题翻译：激光水平
公开(公告)号：USD547215S1
公开(公告)日：2007-07-24
申请号：US29271427
申请日：2007-01-18
申请人： Gregory S. Snider
设计人： Gregory S. Snider

42. 发明授权

US07021637B2 Work box 失效
标题翻译：工作箱
公开(公告)号：US07021637B2
公开(公告)日：2006-04-04
申请号：US10633746
申请日：2003-08-04
申请人： Gregory S. Snider , Jason Busschaert , Clifford D. Read , Michael G. Sirois , James E. Pangerc
发明人： Gregory S. Snider , Jason Busschaert , Clifford D. Read , Michael G. Sirois , James E. Pangerc
IPC分类号： B62J1/00
CPC分类号： B25H1/12
摘要： A work box to be combined with a work table has a base with at least one extending side wall enclosing a tool retaining area. An interruption is formed in the base to define a gap for receiving a support on the work table. The support mounts the base and, in turn, the work box onto the support and the work table.
摘要翻译：与工作台组合的工作箱具有至少一个包围工具保持区域的延伸侧壁的底座。在基座中形成中断以限定用于接收工作台上的支撑的间隙。支撑架将底座安装在支架和工作台上，并将工作台依次安装在支架和工作台上。

43. 发明授权

US06952358B2 Molecular wire content addressable memory 有权
标题翻译：分子线内容可寻址记忆
公开(公告)号：US06952358B2
公开(公告)日：2005-10-04
申请号：US10429421
申请日：2003-05-05
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： G11C13/02 , G11C15/00 , G11C15/04
CPC分类号： B82Y10/00 , G11C13/02 , G11C15/00 , G11C15/046 , G11C2213/77 , G11C2213/81 , Y10S977/762 , Y10S977/943
摘要： In one embodiment, a content addressable memory (CAM), includes: a word line driver configured to provide a driving signal; a tag memory including M word lines traversing through the tag memory and intersecting with 2N bit lines, where M and N are each suitable integer values, where each word line and each bit line is a single molecular wire; a search enable circuitry coupled to the word line driver and configured to allow the driving signal to be driven onto a subset of the word lines in the tag memory; and a match detection circuit coupled to the tag memory and configured to detect current flow on the horizontal word lines.
摘要翻译：在一个实施例中，内容可寻址存储器（CAM）包括：字线驱动器，被配置为提供驱动信号; 标签存储器，包括穿过标签存储器并与2N位线相交的M个字线，其中M和N各自是适合的整数值，其中每个字线和每个位线是单分子线; 耦合到字线驱动器并被配置为允许驱动信号被驱动到标签存储器中的字线子集上的搜索使能电路; 以及匹配检测电路，其耦合到所述标签存储器并且被配置为检测所述水平字线上的电流。

44. 发明授权

US06941541B2 Efficient pipelining of synthesized synchronous circuits 失效
标题翻译：合成同步电路的高效流水线
公开(公告)号：US06941541B2
公开(公告)日：2005-09-06
申请号：US10775945
申请日：2004-02-10
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： G06F17/50
CPC分类号： G06F17/5045
摘要： Method and apparatus for generating a pipelined synchronized circuit representation of a program loop. A dependence graph is generated from the program loop. The dependence graph represents operations and registers and connections therebetween. A minimum clock period and initiation interval are determined from the dependence graph. Until a scheduled graph is successfully generated, repeated attempts are made to generate a scheduled graph from operations and registers of the dependence graph using the minimum clock period and the initiation interval. With each failed attempt to generate a scheduled graph, the minimum clock period is increased prior to the next attempt to generate a scheduled graph.
摘要翻译：用于生成程序循环的流水线同步电路表示的方法和装置。从程序循环生成依赖图。依赖图表示其间的操作和寄存器和连接。从依赖图确定最小时钟周期和起始间隔。直到成功生成计划图，进行重复尝试，以使用最小时钟周期和起始间隔从依赖图的操作和寄存器生成计划图。在每次失败的尝试生成预定图表时，在下一次尝试生成调度图之前，最小时钟周期都会增加。

45. 外观设计

USD449444S1 Article carrier 失效
公开(公告)号：USD449444S1
公开(公告)日：2001-10-23
申请号：US29130039
申请日：2000-09-26
申请人： Gregory S. Snider
设计人： Gregory S. Snider

46. 外观设计

USD446018S1 Tool receiving insert 失效
标题翻译：工具接收插件
公开(公告)号：USD446018S1
公开(公告)日：2001-08-07
申请号：US29109163
申请日：1999-08-11
申请人： John P. Streich , Patrick S. Keenan , Gregory S. Snider , James Pangerc , Matthew J. Holland
设计人： John P. Streich , Patrick S. Keenan , Gregory S. Snider , James Pangerc , Matthew J. Holland

47. 发明授权

US08332340B2 Hybrid microscale-nanoscale neuromorphic integrated circuit 有权
标题翻译：混合微纳米级神经元集成电路
公开(公告)号：US08332340B2
公开(公告)日：2012-12-11
申请号：US12743781
申请日：2008-05-22
申请人： Gregory S. Snider
发明人： Gregory S. Snider
IPC分类号： G06N5/00
CPC分类号： G06N3/063 , G06N3/0635
摘要： Embodiments of the present invention include hybrid microscale-nanoscale neuromorphic integrated circuits that include an array of analog computational cells fabricated on an integrated-circuit-substrate. The analog electronic circuitry within each computational cell connected to one or more pins of a first type and to one or more pins of a second type that extend approximately vertically from the computational cells. The computational cells are additionally interconnected by one or more nanowire-interconnect layers, each nanowire-interconnect layer including two nanowire sublayers on either side of a memristive sublayer, with each nanowire in each nanowire sublayer of an interconnect layer connected to a single computational-cell pin and to a number of nanowires in the other nanowire sublayer of the interconnect layer.
摘要翻译：本发明的实施例包括包含在集成电路基板上制造的模拟计算单元阵列的混合微纳米级纳米级神经元集成电路。每个计算单元内的模拟电子电路连接到第一类型的一个或多个引脚，并且连接到从计算单元大致垂直延伸的第二类型的一个或多个引脚。计算单元另外通过一个或多个纳米线互连层互连，每个纳米线互连层包括在忆阻子层的任一侧上的两个纳米线子层，互连层的每个纳米线子层中的每个纳米线连接到单个计算单元引脚和互连层的另一个纳米线子层中的多个纳米线。

48. 发明授权

US07833842B2 Mixed-scale electronic interface 失效
标题翻译：混合电子接口
公开(公告)号：US07833842B2
公开(公告)日：2010-11-16
申请号：US12630076
申请日：2009-12-03
申请人： R. Stanley Williams , Gregory S. Snider , Duncan Stewart
发明人： R. Stanley Williams , Gregory S. Snider , Duncan Stewart
IPC分类号： H01L21/82
CPC分类号： H01L29/0665 , B82Y10/00 , G11C2213/81 , H01H1/0094 , H01L27/285 , H01L29/0673 , H01L29/0676 , H01L51/0591 , H01L51/0595
摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer.
摘要翻译：本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口，其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。提供了一种用于制造具有微米级和主要为纳米尺度层的纳米尺度/微米界面的方法。

49. 发明授权

US07763978B2 Three-dimensional crossbar array systems and methods for writing information to and reading information stored in three-dimensional crossbar array junctions 有权
标题翻译：用于将信息写入和读取存储在三维交叉列阵列结点中的信息的三维交叉列阵列系统和方法
公开(公告)号：US07763978B2
公开(公告)日：2010-07-27
申请号：US11729228
申请日：2007-03-28
申请人： Wei Wu , R. Stanley Williams , Warren Robinett , Gregory S. Snider , Zhaoning Yu , Shih-Yuan Wang , Duncan Stewart
发明人： Wei Wu , R. Stanley Williams , Warren Robinett , Gregory S. Snider , Zhaoning Yu , Shih-Yuan Wang , Duncan Stewart
IPC分类号： H01L23/52 , H01L23/48 , H01L29/40
CPC分类号： H01L27/101 , B82Y10/00 , G11C13/00 , G11C13/0023 , G11C13/0033 , G11C2213/71 , G11C2213/79 , G11C2213/81 , H01L2924/0002 , Y10S977/762 , H01L2924/00
摘要： Various embodiments of the present invention are directed to three-dimensional crossbar arrays. In one aspect of the present invention, a three-dimensional crossbar array includes a plurality of crossbar arrays, a first demultiplexer, a second demultiplexer, and a third demultiplexer. Each crossbar array includes a first layer of nanowires, a second layer of nanowires overlaying the first layer of nanowires, and a third layer of nanowires overlaying the second layer of nanowires. The first demultiplexer is configured to address nanowires in the first layer of nanowires of each crossbar array, the second demultiplexer is configured to address nanowires in the second layer of nanowires of each crossbar array, and the third demultiplexer is configured to supply a signal to the nanowires in the third layer of nanowires of each crossbar array.
摘要翻译：本发明的各种实施例涉及三维横杆阵列。在本发明的一个方面，三维交叉开关阵列包括多个交叉开关阵列，第一解复用器，第二解复用器和第三解复用器。每个横杆阵列包括第一纳米线层，覆盖第一纳米线层的第二纳米线层和覆盖第二纳米线层的第三层纳米线。第一解复用器被配置为寻址每个交叉列阵列的纳米线的第一层中的纳米线，第二解复用器被配置为寻址每个交叉列阵列的第二纳米线层中的纳米线，并且第三解复用器被配置为向纳米线在每个交叉列阵列的第三层纳米线中。

50. 发明申请

US20100081238A1 MIXED-SCALE ELECTRONIC INTERFACE 失效
标题翻译：混合尺寸电子接口
公开(公告)号：US20100081238A1
公开(公告)日：2010-04-01
申请号：US12630076
申请日：2009-12-03
申请人： R. Stanley Williams , Gregory S. Snider , Duncan Stewart
发明人： R. Stanley Williams , Gregory S. Snider , Duncan Stewart
IPC分类号： H01L21/77
CPC分类号： H01L29/0665 , B82Y10/00 , G11C2213/81 , H01H1/0094 , H01L27/285 , H01L29/0673 , H01L29/0676 , H01L51/0591 , H01L51/0595
摘要： Embodiments of the present invention are directed to mixed-scale electronic interfaces, included in integrated circuits and other electronic devices, that provide for dense electrical interconnection between microscale features of a predominantly microscale or submicroscale layer and nanoscale features of a predominantly nanoscale layer. A method is provided for fabricating a nanoscale/microscale interface having a microscale layer and a predominantly nanoscale layer.
摘要翻译：本发明的实施例涉及包括在集成电路和其他电子设备中的混合比例电子接口，其提供主要是微米级或亚微米级的微尺度特征之间的密集电互连以及主要为纳米尺度层的纳米尺度特征。提供了一种用于制造具有微米级和主要为纳米尺度层的纳米尺度/微米界面的方法。

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