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41. 发明授权

US07843720B2 Phase change memory and method discharging bitline 有权
标题翻译：相变记忆和方法放电位线
公开(公告)号：US07843720B2
公开(公告)日：2010-11-30
申请号：US12256564
申请日：2008-10-23
申请人： Hye-jin Kim , Sang-ki Hwang
发明人： Hye-jin Kim , Sang-ki Hwang
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C13/0004 , G11C13/0023 , G11C13/0026 , G11C2213/72 , G11C2213/79
摘要： Disclosed are a phase change memory device in which an active time is reduced and a method of discharging a bitline in the phase change memory device. In the phase change memory device having the reduced active time and the method of discharging the bitline in the phase change memory device, the bitline is either always discharged when the phase change memory device is in standby, is discharged after the active operation of the phase change memory device, or is discharged prior to and after the active operation of the phase change memory device.
摘要翻译：公开了其中有效时间减少的相变存储器件以及在相变存储器件中放电位线的方法。在相变存储器件中具有减小的有效时间的相变存储器件和放电位线的方法中，当相变存储器件处于待机状态时，位线或者总是被放电，在相位的有效操作之后被放电更换存储器件，或在相变存储器件的有效操作之前和之后被放电。

42. 发明申请

US20100270689A1 Semiconductor packages and electronic systems including the same 有权
标题翻译：半导体封装和电子系统包括相同的
公开(公告)号：US20100270689A1
公开(公告)日：2010-10-28
申请号：US12659775
申请日：2010-03-22
申请人： Hye-jin Kim , Byung-seo Kim , Sun-il Youn
发明人： Hye-jin Kim , Byung-seo Kim , Sun-il Youn
IPC分类号： H01L23/48
CPC分类号： H01L25/0657 , H01L24/48 , H01L24/49 , H01L25/18 , H01L2224/05553 , H01L2224/32145 , H01L2224/32225 , H01L2224/48091 , H01L2224/48145 , H01L2224/48147 , H01L2224/4911 , H01L2225/06506 , H01L2225/06527 , H01L2225/06562 , H01L2924/00014 , H01L2924/01033 , H01L2924/01047 , H01L2924/014 , H01L2924/15311 , H01L2924/181 , H01L2224/45099 , H01L2224/05599 , H01L2924/00012
摘要： Provided are semiconductor packages and electronic systems including the same. A substrate is provided. A plurality of semiconductor chips may be stacked the substrate, and each of them may include at least one electrode pad. At least one of the plurality of semiconductor chips may include at least one redistribution pad configured to electrically connect with the at least one electrode pad.
摘要翻译：提供半导体封装和包括其的电子系统。提供基板。多个半导体芯片可以堆叠在基板上，并且它们中的每一个可以包括至少一个电极焊盘。多个半导体芯片中的至少一个可以包括被配置为与至少一个电极焊盘电连接的至少一个再分布焊盘。

43. 发明申请

US20100128516A1 Nonvolatile Memory Devices Having Bit Line Discharge Control Circuits Therein that Provide Equivalent Bit Line Discharge Control 有权
标题翻译：具有位线放电控制电路的非易失性存储器件，其提供等效的位线放电控制
公开(公告)号：US20100128516A1
公开(公告)日：2010-05-27
申请号：US12323583
申请日：2008-11-26
申请人： Beak-hyung Cho , Yong-seok Jeon , Hye-jin Kim
发明人： Beak-hyung Cho , Yong-seok Jeon , Hye-jin Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/12 , G11C7/18 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2213/72
摘要： A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines.
摘要翻译：存储器件包括其中具有多个行和列的非易失性存储器单元（例如，PRAM单元）的存储器阵列和电耦合到存储器阵列中的对应的第一多列存储器单元的第一多个局部位线。还提供了响应于位线选择信号的第一多个位线选择电路。第一多个位线放电电路电连接到第一多个局部位线中的相应的位线。提供位线放电控制电路以在操作期间用等效的位线放电信号驱动第一多个位线放电电路，以从第一多个局部位线中的所选择的一个读取数据。

44. 发明授权

US07548446B2 Phase change memory device and associated wordline driving circuit 失效
标题翻译：相变存储器件和相关的字线驱动电路
公开(公告)号：US07548446B2
公开(公告)日：2009-06-16
申请号：US11319604
申请日：2005-12-29
申请人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
发明人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028
摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.
摘要翻译：半导体存储器件包括多个字线驱动电路，其适于响应于全局字线和地址信号的逻辑状态来控制子字线的电压电平。字线驱动电路包括第一和第二晶体管，其被配置为当全局字线和地址信号具有第一逻辑状态并且当全局字线或地址信号具有第一电压电平时，将子字线保持在第一电压电平第二逻辑状态。

45. 发明授权

US07391669B2 Semiconductor memory device and core layout thereof 失效
标题翻译：半导体存储器件及其核心布局
公开(公告)号：US07391669B2
公开(公告)日：2008-06-24
申请号：US11316878
申请日：2005-12-27
申请人： Hye-jin Kim , Choong-keun Kwak , Woo-yeong Cho , Sang-beom Kang
发明人： Hye-jin Kim , Choong-keun Kwak , Woo-yeong Cho , Sang-beom Kang
IPC分类号： G11C8/00
CPC分类号： G11C13/0028 , G11C13/0004
摘要： A semiconductor memory device of one aspect includes a memory cell block including n global word lines, and corresponding m sub word lines for each of the n global word lines, where n and m are natural numbers. The memory device further includes a plurality of word line driving circuits which respectively control a voltage of the sub word lines according to a logic level of each corresponding global word line and inputted address signals, and a plurality of control circuits which transmit the address signals to the word line driving circuits or interrupt transmission of the address signals according to the logic level of the global word line. Each of the word line driving circuits includes a first transistor which maintains the voltage of the respective sub word line at a first voltage and a second transistor which maintains the voltage of the sub word line at the first voltage or a second voltage.
摘要翻译：一个方面的半导体存储器件包括包括n个全局字线的存储单元块，以及n个全局字线中的每一个的对应m个子字线，其中n和m是自然数。存储装置还包括多个字线驱动电路，其分别根据每个对应的全局字线和输入的地址信号的逻辑电平分别控制子字线的电压，以及多个控制电路，其将地址信号发送到字线驱动电路或根据全局字线的逻辑电平中断地址信号的传输。每个字线驱动电路包括将相应子字线的电压维持在第一电压的第一晶体管和将子字线的电压维持在第一电压或第二电压的第二晶体管。

46. 发明申请

US20070243197A1 Dendrite Cells Transduced with Recombinant Adenovirus Advcea Which Generate Cea-Specific Cytotoxic T Lymphocytes, Vaccine and Pharmaceutical Composition Comprising the Same 有权
标题翻译：用产生特异性细胞毒性T淋巴细胞的重组腺病毒Advaca转导的树枝状细胞，包含其的疫苗和药物组合物
公开(公告)号：US20070243197A1
公开(公告)日：2007-10-18
申请号：US11570282
申请日：2004-06-11
申请人： Tai-gyu Kim , Hyun-il Cho , Hye-jin Kim , Seoug-taek Oh
发明人： Tai-gyu Kim , Hyun-il Cho , Hye-jin Kim , Seoug-taek Oh
IPC分类号： A61K39/00 , C12N5/16 , C12N7/01
CPC分类号： C07K14/70503 , A61K48/00 , A61K2039/5158 , A61K2039/53 , C12N2710/10043
摘要： The present invention relates to an antitumor immune response, and in more detail, to a method for inducing cytotoxic T lymphocytes specific to a tumor-associated antigen that acts specifically on tumor cells. Immunotherapy using the present invention may be most effective among immune therapies that use immunity of our body, because in the present invention, CEA-specific cytotoxic T lymphocytes can be induced in vitro by using a dendritic cell transduced with a recombinant adenovirus. Further, immunotherapy using the present invention can function as a powerful tool for tumor prevention or treatment, if being used in combination with antitumor vaccines or other treatments.
摘要翻译：本发明涉及抗肿瘤免疫应答，并且更详细地涉及诱导特异性作用于肿瘤细胞的肿瘤相关抗原特异性的细胞毒性T淋巴细胞的方法。使用本发明的免疫治疗在使用我们身体免疫的免疫疗法中可能是最有效的，因为在本发明中，可以通过使用用重组腺病毒转导的树突状细胞在体外诱导CEA特异性细胞毒性T淋巴细胞。此外，如果与抗肿瘤疫苗或其他治疗组合使用，则使用本发明的免疫治疗可用作肿瘤预防或治疗的有力工具。

47. 发明申请

US20070217253A1 Non-volatile phase-change memory device and associated program-suspend-read operation 有权
标题翻译：非易失性相变存储器件和相关的程序挂起读操作
公开(公告)号：US20070217253A1
公开(公告)日：2007-09-20
申请号：US11486100
申请日：2006-07-14
申请人： Hye-jin Kim , Kwang-jin Lee , Sang-Beom Kang , Mu-hui Park
发明人： Hye-jin Kim , Kwang-jin Lee , Sang-Beom Kang , Mu-hui Park
IPC分类号： G11C11/00
CPC分类号： G11C8/12 , G11C11/5678 , G11C13/0004 , G11C13/0061 , G11C13/0069 , G11C2013/0078
摘要： A method of performing a program-suspend-read operation in a PRAM device comprises programming a write block comprising N unit program blocks in response to a program operation request, and suspending the program operation after programming M unit program blocks, where M is less than N, in response to a read operation request. The method further comprises executing the requested read operation, and then resuming the programming of the write data block and programming (N−M) remaining unit program blocks.
摘要翻译：一种在PRAM设备中执行程序挂起读取操作的方法包括响应于程序操作请求编程包含N个单元程序块的写入块，并且在对M个单元程序块进行编程之后暂停编程操作，其中M小于 N，响应于读取操作请求。该方法还包括执行所请求的读取操作，然后恢复写入数据块和编程（N-M）剩余单元程序块的编程。

48. 发明授权

US09019414B2 Method, apparatus, and computer-readable storage medium for selecting operation mode based on reference photographing setting 有权
标题翻译：用于基于参考拍摄设置选择操作模式的方法，装置和计算机可读存储介质
公开(公告)号：US09019414B2
公开(公告)日：2015-04-28
申请号：US13555507
申请日：2012-07-23
申请人： Jung-ah Heo , Se-hyun Park , Hye-jin Kim
发明人： Jung-ah Heo , Se-hyun Park , Hye-jin Kim
IPC分类号： H04N5/222 , H04N5/232
CPC分类号： H04N5/232
摘要： A digital photographing apparatus controlling method includes: providing menus for respectively adjusting a reference photographing setting value and first group photographing setting values; and setting an operation mode according to which one of the reference photographing setting value and the first group photographing setting values a user has selected.
摘要翻译：数字拍摄装置控制方法包括：提供用于分别调整参考拍摄设置值和第一组拍摄设置值的菜单; 并且根据用户选择的参考拍摄设置值和第一组拍摄设置值中的哪一个来设置操作模式。

49. 发明授权

US08902345B2 Method and apparatus for synthesizing two or more images together with one another via divided display screen 有权
标题翻译：用于通过划分的显示屏幕彼此合成两个或多个图像的方法和装置
公开(公告)号：US08902345B2
公开(公告)日：2014-12-02
申请号：US13603592
申请日：2012-09-05
申请人： Wan-je Park , Hye-jin Kim , Tai-hoon Kim
发明人： Wan-je Park , Hye-jin Kim , Tai-hoon Kim
IPC分类号： H04N5/222
CPC分类号： H04N5/23293 , H04N5/2621
摘要： A digital photographing apparatus and a method of controlling the same. The method including setting a division frame configured by dividing a display screen; displaying a first input image in a first region of the set division frame; displaying the first input image captured according to a first photographing signal, in the first region; displaying a second input image in a second region of the set division frame; and displaying the second input image captured according to a second photographing signal in the second region.
摘要翻译：数字摄影装置及其控制方法。该方法包括：设置通过划分显示画面而构成的分割帧; 在所述设定分割帧的第一区域中显示第一输入图像; 在第一区域中显示根据第一拍摄信号拍摄的第一输入图像; 在所述设定分割帧的第二区域中显示第二输入图像; 以及在第二区域中显示根据第二拍摄信号捕获的第二输入图像。

50. 发明授权

US08526223B2 Phase change random access memory device and related methods of operation 有权
标题翻译：相变随机存取存储器件及相关操作方法
公开(公告)号：US08526223B2
公开(公告)日：2013-09-03
申请号：US13655666
申请日：2012-10-19
申请人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim
发明人： Hye-jin Kim , Kwang-jin Lee , Du-eung Kim
IPC分类号： G11C11/00
CPC分类号： G11C13/0064 , G11C11/5678 , G11C13/0004 , G11C13/0069 , G11C2013/0092
摘要： A method of operating a phase change random access memory (PRAM) device includes performing a program operation to store data in selected PRAM cells of the device, wherein the program operation comprises a plurality of sequential program loops. The method further comprises suspending the program operation in the middle of the program operation, and after suspending the program operation, resuming the program operation in response to a resume command.
摘要翻译：操作相变随机存取存储器（PRAM）装置的方法包括执行程序操作以将数据存储在所述装置的所选PRAM单元中，其中所述程序操作包括多个顺序程序循环。该方法还包括在编程操作的中间暂停编程操作，并且在暂停编程操作之后，响应于恢复命令恢复程序操作。

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