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1. 发明申请

US20100128516A1 Nonvolatile Memory Devices Having Bit Line Discharge Control Circuits Therein that Provide Equivalent Bit Line Discharge Control 有权
标题翻译：具有位线放电控制电路的非易失性存储器件，其提供等效的位线放电控制
公开(公告)号：US20100128516A1
公开(公告)日：2010-05-27
申请号：US12323583
申请日：2008-11-26
申请人： Beak-hyung Cho , Yong-seok Jeon , Hye-jin Kim
发明人： Beak-hyung Cho , Yong-seok Jeon , Hye-jin Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C7/12 , G11C7/18 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2213/72
摘要： A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines.
摘要翻译：存储器件包括其中具有多个行和列的非易失性存储器单元（例如，PRAM单元）的存储器阵列和电耦合到存储器阵列中的对应的第一多列存储器单元的第一多个局部位线。还提供了响应于位线选择信号的第一多个位线选择电路。第一多个位线放电电路电连接到第一多个局部位线中的相应的位线。提供位线放电控制电路以在操作期间用等效的位线放电信号驱动第一多个位线放电电路，以从第一多个局部位线中的所选择的一个读取数据。

2. 发明授权

US08040719B2 Nonvolatile memory devices having bit line discharge control circuits therein that provide equivalent bit line discharge control 有权
标题翻译：其中具有提供等效位线放电控制的位线放电控制电路的非易失性存储器件
公开(公告)号：US08040719B2
公开(公告)日：2011-10-18
申请号：US12323583
申请日：2008-11-26
申请人： Beak-hyung Cho , Yong-seok Jeon , Hye-jin Kim
发明人： Beak-hyung Cho , Yong-seok Jeon , Hye-jin Kim
IPC分类号： G11C11/00
CPC分类号： G11C7/12 , G11C7/18 , G11C13/0004 , G11C13/0026 , G11C13/004 , G11C2213/72
摘要： A memory device includes a memory array having a plurality of rows and columns of nonvolatile memory cells (e.g., PRAM cells) therein and a first plurality of local bit lines electrically coupled to a corresponding first plurality of columns of memory cells in the memory array. A first plurality of bit line selection circuits are also provided, which are responsive to bit line selection signals. A first plurality of bit line discharge circuits are electrically connected to respective ones of the first plurality of local bit lines. A bit line discharge control circuit is provided to drive the first plurality of bit line discharge circuits with equivalent bit line discharge signals during an operation to read data from a selected one of the first plurality of local bit lines.
摘要翻译：存储器件包括其中具有多个行和列的非易失性存储器单元（例如，PRAM单元）的存储器阵列和电耦合到存储器阵列中的对应的第一多列存储器单元的第一多个局部位线。还提供了响应于位线选择信号的第一多个位线选择电路。第一多个位线放电电路电连接到第一多个局部位线中的相应的位线。提供位线放电控制电路以在操作期间用等效的位线放电信号驱动第一多个位线放电电路，以从第一多个局部位线中的所选择的一个读取数据。

3. 发明授权

US07548446B2 Phase change memory device and associated wordline driving circuit 失效
标题翻译：相变存储器件和相关的字线驱动电路
公开(公告)号：US07548446B2
公开(公告)日：2009-06-16
申请号：US11319604
申请日：2005-12-29
申请人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
发明人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
IPC分类号： G11C11/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028
摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.
摘要翻译：半导体存储器件包括多个字线驱动电路，其适于响应于全局字线和地址信号的逻辑状态来控制子字线的电压电平。字线驱动电路包括第一和第二晶体管，其被配置为当全局字线和地址信号具有第一逻辑状态并且当全局字线或地址信号具有第一电压电平时，将子字线保持在第一电压电平第二逻辑状态。

4. 发明申请

US20060209616A1 Phase change memory device and associated wordline driving circuit 失效
公开(公告)号：US20060209616A1
公开(公告)日：2006-09-21
申请号：US11319604
申请日：2005-12-29
申请人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
发明人： Hye-jin Kim , Du-eung Kim , Beak-hyung Cho , Hyung-rok Oh
IPC分类号： G11C8/00
CPC分类号： G11C13/0004 , G11C8/08 , G11C13/0028
摘要： A semiconductor memory device includes a plurality of wordline driving circuits adapted to control the voltage level of a sub-wordline in response to a logic state of a global wordline and an address signal. The wordline driving circuit comprises first and second transistors configured to maintain the sub-wordline at a first voltage level when the global wordline and the address signal have a first logic state and at a second voltage level when the global wordline or the address signal have a second logic state.

5. 发明授权

US07515459B2 Method of programming a memory cell array using successive pulses of increased duration 有权
标题翻译：使用增加的持续时间的连续脉冲对存储器单元阵列进行编程的方法
公开(公告)号：US07515459B2
公开(公告)日：2009-04-07
申请号：US11315129
申请日：2005-12-23
申请人： Sang-beom Kang , Du-eung Kim , Beak-hyung Cho , Hye-jin Kim
发明人： Sang-beom Kang , Du-eung Kim , Beak-hyung Cho , Hye-jin Kim
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C13/0004 , G11C13/0069 , G11C2013/0078 , G11C2013/0092 , G11C2213/79
摘要： A method of programming a memory array including a plurality of memory cells is provided. The memory cells may include phase-change memory elements. In one aspect, the method includes applying in succession first through nth current pulses to each of the memory cells to be programmed to a first state (e.g., a crystalline state), where a current amplitude of the first through nth current pulses decreases with each successive pulse, and where a pulse duration of the first through nth current pulses increases with each successive pulse.
摘要翻译：提供了一种编程包括多个存储单元的存储器阵列的方法。存储器单元可以包括相变存储元件。在一个方面，该方法包括将第一至第n电流脉冲连续地应用于要被编程到第一状态（例如，结晶状态）的每个存储器单元，其中第一至第n电流脉冲的电流幅度随着每个连续脉冲，并且其中第一至第n电流脉冲的脉冲持续时间随着每个连续脉冲而增加。

6. 发明授权

US08243495B2 Phase-change random access memory capable of reducing word line resistance 有权
标题翻译：相位随机存取存储器能够减少字线电阻
公开(公告)号：US08243495B2
公开(公告)日：2012-08-14
申请号：US12379399
申请日：2009-02-20
申请人： Byung-gil Choi , Won-ryul Chung , Beak-hyung Cho
发明人： Byung-gil Choi , Won-ryul Chung , Beak-hyung Cho
IPC分类号： G11C11/00
CPC分类号： G11C5/063 , G11C13/0004 , G11C2213/72
摘要： A phase-change random access memory (PRAM) device capable of reducing a resistance of a word line may include a plurality of main word lines of a semiconductor memory device or PRAM bent n times in a layer different from a layer in which a plurality of sub-word lines are disposed. The semiconductor memory device or PRAM may further include jump contacts for connecting the plurality of cut sub-word lines. In a PRAM device including the plurality of main word lines and the plurality of sub-word lines being in different layers, the number of jump contacts for connecting the plurality of main word lines to a transistor of a sub-word line decoder is the same in each sub-word line or the plurality of main word lines are bent several times so that a parasitic resistance on a word line and power consumption may be reduced, and a sensing margin may be increased.
摘要翻译：能够降低字线的电阻的相变随机存取存储器（PRAM）装置可以包括半导体存储器件的多个主字线或在与多个子字线被排列。半导体存储器件或PRAM还可以包括用于连接多个切割子字线的跳跃触点。在包括多个主字线和多个子字线在不同层中的PRAM装置中，用于将多个主字线连接到子字线解码器的晶体管的跳转触点的数量是相同的在每个子字线或多个主字线被多次弯曲，从而可以减少字线上的寄生电阻和功耗，并且可以增加感测裕度。

7. 发明申请

US20090225590A1 Phase change random access memory 有权
公开(公告)号：US20090225590A1
公开(公告)日：2009-09-10
申请号：US12453420
申请日：2009-05-11
申请人： Hyung-rok Oh , Woo-Yeong Cho , Beak-hyung Cho
发明人： Hyung-rok Oh , Woo-Yeong Cho , Beak-hyung Cho
IPC分类号： G11C11/00 , G11C7/00
CPC分类号： G11C8/10 , G11C13/0004 , G11C13/004 , G11C2013/0054
摘要： Provided is a phase change random access (PRAM) memory. The PRAM may include a memory cell array having a plurality of phase change memory cells, and a data read circuit including a compensation unit and a sense amplifier, the compensation unit configured to provide a sensing node with a compensation current to compensate for a decrease in a level of the sensing node caused by a current flowing through one of the plurality of phase change memory cells, and the sense amplifier configured to compare a level of the sensing node with a reference level and output a result of the comparison.

8. 发明申请

US20080158941A1 Nonvolatile memory device using variable resistive elements 有权
标题翻译：使用可变电阻元件的非易失性存储器件
公开(公告)号：US20080158941A1
公开(公告)日：2008-07-03
申请号：US12003442
申请日：2007-12-26
申请人： Byung-gil Choi , Beak-hyung Cho
发明人： Byung-gil Choi , Beak-hyung Cho
IPC分类号： G11C11/00 , G11C7/00 , G11C8/00
CPC分类号： G11C7/18 , G11C13/0004 , G11C2029/2602 , H01L27/24
摘要： The nonvolatile memory device includes a plurality of memory banks, each of which includes a plurality of nonvolatile memory cells. Each cell includes a variable resistive element having a resistance varying depending on stored data. A plurality of global bit lines are included, and each global bit line is shared by the plurality of memory banks. A plurality of main word lines are arranged corresponding to one of the plurality of memory banks.
摘要翻译：非易失性存储器件包括多个存储体，每个存储体包括多个非易失性存储单元。每个单元包括具有根据存储的数据而变化的电阻的可变电阻元件。包括多个全局位线，并且每个全局位线被多个存储体共享。多个主字线被布置成与多个存储体之一相对应。

9. 发明授权

US07236393B2 Phase-change semiconductor memory device and method of programming same 有权
标题翻译：相变半导体存储器件及其编程方法
公开(公告)号：US07236393B2
公开(公告)日：2007-06-26
申请号：US11254853
申请日：2005-10-21
申请人： Beak-hyung Cho , Choong-keun Kwak
发明人： Beak-hyung Cho , Choong-keun Kwak
IPC分类号： G11C11/00
CPC分类号： G11C13/003 , G11C13/0004 , G11C13/0069 , G11C2213/78 , G11C2213/79
摘要： A semiconductor memory device and a method of programming the same, the semiconductor memory device includes a plurality of memory cells, each of the memory cells having a plurality of phase change variable resistors and a selection transistor. Each of the phase change variable resistors has a first end connected to one of a plurality of bit lines and a second end connected to a drain of the selection transistor. The selection transistor has a gate connected to a word line and a source connected to a reference voltage. The memory device is programmed by activating a word line associated with a selected memory cell, thereby turning on the selection transistor, applying a reset pulse to bit lines of the selected memory cell, and applying a set pulse to selected bit lines of the selected memory cell.
摘要翻译：半导体存储器件及其编程方法，半导体存储器件包括多个存储器单元，每个存储器单元具有多个相变可变电阻器和选择晶体管。每个相变可变电阻器具有连接到多个位线之一的第一端和连接到选择晶体管的漏极的第二端。选择晶体管具有连接到字线的栅极和连接到参考电压的源极。通过激活与所选择的存储器单元相关联的字线来编程存储器件，从而导通选择晶体管，将复位脉冲施加到所选存储单元的位线，以及将设置的脉冲施加到所选存储器的选定位线细胞。

10. 发明申请

US20060291277A1 Phase change random access memory (PRAM) device 有权
公开(公告)号：US20060291277A1
公开(公告)日：2006-12-28
申请号：US11315347
申请日：2005-12-23
申请人： Beak-hyung Cho , Kwang-jin Lee , Mu-hui Park
发明人： Beak-hyung Cho , Kwang-jin Lee , Mu-hui Park
IPC分类号： G11C11/00
CPC分类号： G11C11/5678 , G11C7/12 , G11C13/0004 , G11C13/0028 , G11C2213/72
摘要： A phase change memory device has a word line driver layout which allows for a reduction in the size a core area of the device. In one aspect, phase change memory device includes a plurality of memory cell blocks sharing a word line, and a plurality of word line drivers driving the word line. Each of the word line drivers includes a precharge device for precharging the word line and a discharge device for discharging the word line, and where the precharge device and the discharge device are alternately located between the plurality of memory cell blocks.

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