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41. 发明申请

US20140342486A1 ELEMENTAL SEMICONDUCTOR MATERIAL CONTACT FOR GaN-BASED LIGHT EMITTING DIODES 审中-公开
标题翻译：用于GaN基发光二极管的元素半导体材料接触
公开(公告)号：US20140342486A1
公开(公告)日：2014-11-20
申请号：US14019733
申请日：2013-09-06
申请人： International Business Machines Corporation
发明人： Anirban Basu , Bahman Hekmatshoartabari , Davood Shahrjerdi
IPC分类号： H01L33/06
CPC分类号： H01L33/06 , H01L33/0075 , H01L33/02 , H01L33/20 , H01L33/32 , H01L2933/0016
摘要： A vertical stack including a p-doped GaN portion, a multi-quantum-well, and an n-doped GaN portion is formed on an insulator substrate. The p-doped GaN portion may be formed above, or below, the multi-quantum-well. A dielectric material liner is formed around the vertical stack, and is patterned to physically expose a top surface of the p-doped GaN portion. A selective low temperature epitaxy process is employed to deposit a semiconductor material including at least one elemental semiconductor material on the physically exposed surfaces of the p-doped GaN portion, thereby forming an elemental semiconductor material portion. Metallization is performed on a portion of the elemental semiconductor material portions to form an electrical contact structure that provides effective electrical contact to the p-doped GaN portion through the elemental semiconductor material portion. The elemental semiconductor material portion spreads electrical current between the electrical contact structure and the p-doped GaN portion.
摘要翻译：包括p掺杂GaN部分，多量子阱和n掺杂GaN部分的垂直堆叠形成在绝缘体基板上。 p掺杂的GaN部分可以形成在多量子阱的上方或下方。在垂直叠层周围形成电介质材料衬垫，并被图案化以物理暴露p掺杂GaN部分的顶表面。采用选择性低温外延工艺将包含至少一种元素半导体材料的半导体材料沉积在p掺杂GaN部分的物理暴露表面上，从而形成元素半导体材料部分。在元素半导体材料部分的一部分上进行金属化以形成通过元素半导体材料部分向p掺杂的GaN部分提供有效的电接触的电接触结构。元素半导体材料部分在电接触结构和p掺杂GaN部分之间扩展电流。

42. 发明申请

US20140252448A1 EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP 有权
公开(公告)号：US20140252448A1
公开(公告)日：2014-09-11
申请号：US14029171
申请日：2013-09-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stephen W. Bedell , Bahman Hekmatshoar-Tabari , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L29/786
CPC分类号： H01L29/66825 , H01L21/84 , H01L27/11531 , H01L27/1203 , H01L29/78603 , H01L29/78654 , H01L29/788 , H01L29/7881
摘要： A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device.

43. 发明申请

US20140252446A1 EXTREMELY THIN SEMICONDUCTOR ON INSULATOR (ETSOI) LOGIC AND MEMORY HYBRID CHIP 有权
标题翻译：绝缘子（ETSOI）超薄半导体逻辑和存储器混合芯片
公开(公告)号：US20140252446A1
公开(公告)日：2014-09-11
申请号：US13791554
申请日：2013-03-08
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stephen W. Bedell , Bahman Hekmatshoar-Tabari , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L29/66 , H01L29/788
CPC分类号： H01L29/66825 , H01L21/84 , H01L27/11531 , H01L27/1203 , H01L29/78603 , H01L29/78654 , H01L29/788 , H01L29/7881
摘要： A method of forming a semiconductor device that includes providing a logic device on a semiconductor on insulating layer of a transfer substrate. The transfer substrate may further include a dielectric layer and a first handle substrate. A second handle substrate may be contacted to the semiconductor on insulating layer of the transfer substrate that includes logic device. The first handle substrate may be removed to expose the dielectric layer. A memory device can then be formed on the dielectric layer. Interconnect wiring can then be formed connecting the logic device with the memory device.
摘要翻译：一种形成半导体器件的方法，包括在转移衬底的绝缘层上的半导体上提供逻辑器件。转移基板还可以包括介电层和第一手柄基板。第二处理衬底可以与包括逻辑器件的转移衬底的绝缘层上的半导体接触。可以去除第一处理衬底以暴露电介质层。然后可以在电介质层上形成存储器件。然后可以形成连接逻辑器件与存储器件的互连接线。

44. 发明申请

US20140131803A1 ON-CHIP DIODE WITH FULLY DEPLETED SEMICONDUCTOR DEVICES 有权
标题翻译：带有全部半导体器件的片上二极管
公开(公告)号：US20140131803A1
公开(公告)日：2014-05-15
申请号：US13677610
申请日：2012-11-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L27/12
CPC分类号： H01L21/84 , H01L21/823814 , H01L21/845 , H01L27/0629 , H01L27/1203 , H01L27/1211 , H01L27/1214 , H01L27/1255 , H01L27/1259 , H01L29/861
摘要： An electrical device including a first conductivity semiconductor device present in a first semiconductor device region of an SOI substrate, and a second conductivity semiconductor device present in a second semiconductor device region of the SOI substrate. The electrical device also includes a diode present within a diode region of the SOI substrate that includes a first doped layer of a first conductivity semiconductor material that is present on an SOI layer of the SOI substrate. The first doped layer includes a first plurality of protrusions extending from a first connecting base portion. The semiconductor diode further includes a second doped layer of the second conductivity semiconductor material present over the first doped layer. The second doped layer including a second plurality of protrusions extending from a second connecting base portion. The second plurality of protrusions is present between and separating the first plurality of protrusions
摘要翻译：一种电气装置，包括存在于SOI衬底的第一半导体器件区域中的第一导电半导体器件和存在于SOI衬底的第二半导体器件区域中的第二导电半导体器件。电子器件还包括存在于SOI衬底的二极管区域内的二极管，其包括存在于SOI衬底的SOI层上的第一导电半导体材料的第一掺杂层。第一掺杂层包括从第一连接基部延伸的第一多个突起。半导体二极管还包括存在于第一掺杂层上的第二导电半导体材料的第二掺杂层。第二掺杂层包括从第二连接基部延伸的第二多个突起。第二多个突起存在于并分离第一多个突起之间

45. 发明申请

US20140103436A1 EXTREMELY THIN SEMICONDUCTOR-ON-INSULATOR WITH BACK GATE CONTACT 有权
公开(公告)号：US20140103436A1
公开(公告)日：2014-04-17
申请号：US13651874
申请日：2012-10-15
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L27/12 , H01L21/04
CPC分类号： H01L21/7624 , H01L21/743 , H01L21/76898 , H01L21/84 , H01L29/78603 , H01L29/78648 , H01L29/78696
摘要： A structure is provided in which the back gate regions are physically separated from one another as opposed to using reversed biased pn junction diodes. In the present disclosure, the back gate regions can be formed first through a buried dielectric material of an extremely thin semiconductor-on-insulator (ETSOI) substrate. After dopant activation, standard device fabrication processes can be performed. A semiconductor base layer portion of the ETSOI substrate can then be removed from the original ETSOI to expose a surface of the back gates.

46. 发明申请

US20130260505A1 SOLAR-POWERED ENERGY-AUTONOMOUS SILICON-ON-INSULATOR DEVICE 有权
公开(公告)号：US20130260505A1
公开(公告)日：2013-10-03
申请号：US13717684
申请日：2012-12-17
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Stephen W. Bedell , Bahman Hekmatshoartabari , Devendra K. Sadana , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： H01L31/18
CPC分类号： H01L27/142 , H01L21/84 , H01L27/092 , H01L27/1203 , H01L31/0504 , H01L31/068 , H01L31/1892 , Y02E10/547
摘要： A solar-powered autonomous CMOS circuit structure is fabricated with monolithically integrated photovoltaic solar cells. The structure includes a device layer including an integrated circuit and a solar cell layer. Solar cell structures in the solar cell layer can be series connected during metallization of the device layer or subsequently. The device layer and the solar cell layer are formed using a silicon-on-insulator substrate. Subsequent spalling of the silicon-on-insulator substrate through the handle substrate thereof facilitates production of a relatively thin solar cell layer that can be subjected to a selective etching process to isolate the solar cell structures.

47. 发明授权

US11378545B2 Nanofluid sensor with real-time spatial sensing 有权
公开(公告)号：US11378545B2
公开(公告)日：2022-07-05
申请号：US16794995
申请日：2020-02-19
申请人： International Business Machines Corporation
发明人： Kangguo Cheng , Ali Khakifirooz , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： G01N27/414 , H01L27/12 , H01L21/84
摘要： A semiconductor structure capable of real-time spatial sensing of nanoparticles within a nanofluid is provided. The structure includes an array of gate structures. An interlevel dielectric material surrounds the array of gate structures. A vertical inlet channel is located within a portion of the interlevel dielectric material and on one side of the array of gate structures. A vertical outlet channel is located within another portion of the interlevel dielectric material and on another side of the array of gate structures. A horizontal channel that functions as a back gate is in fluid communication with the vertical inlet and outlet channels, and is located beneath the array of gate structures. A back gate dielectric material portion lines exposed surfaces within the vertical inlet channel, the vertical outlet channel and the horizontal channel.

48. 发明授权

US10772720B2 Method of assembling artificial electronic skin 有权
公开(公告)号：US10772720B2
公开(公告)日：2020-09-15
申请号：US15978129
申请日：2018-05-12
申请人： International Business Machines Corporation
发明人： Bahman Hekmatshoartabari , Ghavam G. Shahidi , Davood Shahrjerdi
IPC分类号： G01R31/28 , A61F2/10 , H01L29/06 , H01L29/16 , H01L27/12 , A61F2/50 , H01L21/3213 , A61F2/76 , G01L5/22 , H01L23/498 , A61F2/70 , A61F2/68 , B82Y15/00
摘要： High resolution active matrix nanowire circuits enable a flexible platform for artificial electronic skin having pressure sensing capability. Comb-like interdigitated nanostructures extending vertically from a pair of opposing, flexible assemblies facilitate pressure sensing via changes in resistance caused by varying the extent of contact among the interdigitated nanostructures. Electrically isolated arrays of vertically extending, electrically conductive nanowires or nanofins are formed from a doped, electrically conductive layer, each of the arrays being electrically connected to a transistor in an array of transistors. The nanowires or nanofins are interdigitated with further electrically conductive nanowires or nanofins mounted to a flexible handle.

49. 发明申请

US20190288146A1 SOLAR CELL WITH BORDERLESS INTERDIGITATED CONTACTS AND METHOD OF MAKING 审中-公开
公开(公告)号：US20190288146A1
公开(公告)日：2019-09-19
申请号：US16429568
申请日：2019-06-03
申请人： International Business Machines Corporation
发明人： Joel P. De Souza , Harold John Hovel , Daniel Inns , Jeehwan Kim , Christian Lavoie , Devendra K. Sadana , Katherine L. Saenger , Davood Shahrjerdi , Zhen Zhang
IPC分类号： H01L31/068 , H01L31/18 , H01L31/0224
摘要： A solar cell having n-type and p-type interdigitated back contacts (IBCs), which cover the entire back surface of the absorber layer. The spatial separation of the IBCs is in a direction perpendicular to the back surface, thus providing borderless contacts having a zero-footprint separation. As the contacts are on the back, photons incident on the cell's front surface can be absorbed without any shadowing.

50. 发明申请

US20190279946A1 MONOLITHIC INTEGRATION OF III-V CELLS FOR POWERING MEMORY ERASURE DEVICES 审中-公开
公开(公告)号：US20190279946A1
公开(公告)日：2019-09-12
申请号：US16420567
申请日：2019-05-23
申请人： International Business Machines Corporation
发明人： Kenneth Rodbell , Davood Shahrjerdi
IPC分类号： H01L23/00 , H01L27/144 , H01L31/18 , H01L31/0693 , H01L27/142 , G06F21/87
摘要： A method for making a photovoltaic device is provided that includes the steps of providing a silicon substrate having a complementary metal-oxide semiconductor (“CMOS”); bonding a first layer of silicon oxide to a second layer of silicon oxide wherein the bonded layers are deposited on the silicon substrate; and forming a III-V photovoltaic cell on a side of the bonded silicon oxide layers opposite the silicon substrate, wherein when the III-V photovoltaic cell is exposed to radiation, the III-V photovoltaic cell generates a current that powers a memory erasure device to cause an alteration of a memory state of a memory cell in an integrated circuit.

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