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    • 41. 发明授权
    • Coding apparatus, decoding apparatus, amplitude adjustment apparatus, recorded information reader, signal processing apparatus and storage system
    • 编码装置,解码装置,幅度调整装置,记录信息读取器,信号处理装置和存储系统
    • US07812745B2
    • 2010-10-12
    • US12178423
    • 2008-07-23
    • Atsushi EsumiKai Li
    • Atsushi EsumiKai Li
    • H03M7/00
    • G11B20/1426G11B20/10009G11B20/10027G11B20/10055G11B2220/2516H03M5/145
    • A general purpose of the present invention is to improve a DC-free property with a further reduced circuit scale while satisfying a run-length limit. An RLL/DC-free coding unit coding includes a first RLL coding unit, a first signal processing unit, a second RLL coding unit, and a DC component removal coding unit. The first RLL coding unit generates a first coded sequence by subjecting a digital signal sequence outputted from a scrambler to run-length limited coding. The first signal processing unit performs a predetermined signal processing on the digital signal sequence without changing the number of a plurality of bits contained in the digital signal sequence outputted from the scrambler 302. The second RLL coding unit generates a second coded sequence by subjecting the digital signal sequence, which is outputted from the first signal processing unit and on which the predetermined signal processing has been performed by the signal processing unit, to run-length limited coding.
    • 本发明的一般目的是在满足游程长度限制的同时,通过进一步降低的电路规模改善无DC特性。 无RLL / DC编码单元编码包括第一RLL编码单元,第一信号处理单元,第二RLL编码单元和DC分量去除编码单元。 第一RLL编码单元通过对从加扰器输出的数字信号序列进行游程限制编码来产生第一编码序列。 第一信号处理单元对数字信号序列执行预定的信号处理,而不改变从加扰器302输出的数字信号序列中包含的多个位的数目。第二RLL编码单元通过对数字信号 信号序列,其从第一信号处理单元输出并且信号处理单元已经执行了预定信号处理,进行游程限制编码。