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41. 发明授权

US07948699B2 Systems and methods for equalizer optimization in a storage access retry 有权
标题翻译：存储访问重试中均衡器优化的系统和方法
公开(公告)号：US07948699B2
公开(公告)日：2011-05-24
申请号：US12348236
申请日：2009-01-02
申请人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
发明人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： G11B5/09
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10481 , G11B20/18 , G11B2020/183 , G11B2220/2516
摘要： Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
摘要翻译：本发明的各种实施例提供了包括多路复用器，存储器缓冲器，数据处理电路和通道设置修改电路的数据处理电路。多路复用器的第一输入接收输入数据集，多路复用器的第二输入接收缓冲数据集。复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。存储器缓冲器接收多路复用器输出并提供缓冲数据集。数据处理电路的操作至少部分由通道设置决定。数据处理电路接收复用器输出并执行数据检测处理。当数据检测过程失败时，选择信号被置位以选择缓冲数据集，当数据检测过程成功时，选择信号选择输入数据集。当数据检测处理失败时，通道设置修改电路可操作以修改通道设置。

42. 发明授权

US07929237B2 Modulated disk lock clock and methods for using such 有权
标题翻译：调制磁盘锁时钟及使用方法
公开(公告)号：US07929237B2
公开(公告)日：2011-04-19
申请号：US12147543
申请日：2008-06-27
申请人： Jeffrey P. Grundvig , Richard Rauschmayer
发明人： Jeffrey P. Grundvig , Richard Rauschmayer
IPC分类号： G11B5/09 , G11B27/36
CPC分类号： G11B20/14 , G11B20/10222 , G11B2020/1476 , G11B2020/1484 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for controlling access to a magnetic storage medium. As one example, a method for controlling access to a storage medium is disclosed that includes calculating a point to point error amount, and generating a incremental error value based at least in part on the point to point error amount. The incremental error value is applied incrementally across a defined number of clock cycles.
摘要翻译：本发明的各种实施例提供了用于控制对磁存储介质的访问的系统和方法。作为一个示例，公开了一种用于控制对存储介质的访问的方法，其包括计算点对点误差量，并且至少部分地基于点对点误差量生成增量误差值。递增错误值在规定数量的时钟周期内逐步应用。

43. 发明授权

US07924523B2 Frequency domain approach for efficient computation of fixed-point equalization targets 有权
标题翻译：用于有效计算定点均衡目标的频域方法
公开(公告)号：US07924523B2
公开(公告)日：2011-04-12
申请号：US12273265
申请日：2008-11-18
申请人： George Mathew , Yuan Xing Lee , Hongwei Song , Richard Rauschmayer
发明人： George Mathew , Yuan Xing Lee , Hongwei Song , Richard Rauschmayer
IPC分类号： G11B5/035
CPC分类号： G11B20/10212 , G11B20/10046 , G11B20/10194 , G11B20/24 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for equalizing an input signal. For example, various embodiments of the present invention provide a method for performing equalization in a storage device. Such methods include providing an equalizer circuit that is governed by a target value, and a filter circuit that is governed by a filter coefficient. An initial value is provided to the equalizer circuit as the target value, and an overall target based at least in part on the initial value and the filter coefficient is calculated. An updated value is calculated based on the overall target, and the updated value is provided to the equalizer circuit as the target value.
摘要翻译：本发明的各种实施例提供了用于均衡输入信号的系统和方法。例如，本发明的各种实施例提供了一种用于在存储设备中执行均衡的方法。这样的方法包括提供由目标值控制的均衡器电路和由滤波器系数控制的滤波器电路。将初始值作为目标值提供给均衡器电路，并且至少部分地基于初始值和滤波器系数来计算总体目标。基于总体目标计算更新的值，并且将更新的值作为目标值提供给均衡器电路。

44. 发明申请

US20100172046A1 Systems and Methods for Equalizer Optimization in a Storage Access Retry 有权
标题翻译：存储访问重试中均衡器优化的系统和方法
公开(公告)号：US20100172046A1
公开(公告)日：2010-07-08
申请号：US12348236
申请日：2009-01-02
申请人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
发明人： Jingfeng Liu , Hongwei Song , Richard Rauschmayer , Yuan Xing Lee
IPC分类号： G11B20/10
CPC分类号： G11B20/10009 , G11B20/10046 , G11B20/10055 , G11B20/10481 , G11B20/18 , G11B2020/183 , G11B2220/2516
摘要： Various embodiments of the present invention provide data processing circuits that include a multiplexer, a memory buffer, a data processing circuit, and a channel setting modification circuit. A first input of the multiplexer receives an input data set and a second input of the multiplexer receives a buffered data set. The multiplexer provides either the input data set or the buffered data set as a multiplexer output based upon a select signal. The memory buffer receives the multiplexer output and provides the buffered data set. Operation of the data processing circuit is at least in part governed by channel settings. The data processing circuit receives the multiplexer output and performs a data detection process. The select signal is asserted to select the buffered data set when the data detection process fails, and is asserted to select the input data set when the data detection process succeeds. The channel setting modification circuit is operable to modify the channel settings when the data detection process fails.
摘要翻译：本发明的各种实施例提供了包括多路复用器，存储器缓冲器，数据处理电路和通道设置修改电路的数据处理电路。多路复用器的第一输入接收输入数据集，多路复用器的第二输入接收缓冲数据集。复用器根据选择信号提供输入数据组或缓冲数据组作为多路复用器输出。存储器缓冲器接收多路复用器输出并提供缓冲数据集。数据处理电路的操作至少部分由通道设置决定。数据处理电路接收复用器输出并执行数据检测处理。当数据检测过程失败时，选择信号被置位以选择缓冲数据集，当数据检测过程成功时，选择信号选择输入数据集。当数据检测处理失败时，通道设置修改电路可操作以修改通道设置。

45. 发明授权

US07739533B2 Systems and methods for operational power management 失效
标题翻译：操作电源管理的系统和方法
公开(公告)号：US07739533B2
公开(公告)日：2010-06-15
申请号：US11534305
申请日：2006-09-22
申请人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
发明人： Richard Rauschmayer , Steven E. Strauss , Tatsuya Sakai
IPC分类号： G06F1/00 , G06F1/04
CPC分类号： G06F1/3203 , G06F1/04 , G06F1/24 , G06F1/3268 , Y02D10/154
摘要： Various systems and methods for power management are disclosed herein. For example, a synchronous semiconductor circuit is disclosed that includes two or more clock sources and a power management controller. The power management controller is operable to apply power to one of the clock sources and to select another of the clock sources for synchronization of the circuit. Then, upon stabilization of the first clock source, it is selected by the power management controller to synchronize the circuit.
摘要翻译：本文公开了用于电力管理的各种系统和方法。例如，公开了包括两个或更多个时钟源和电源管理控制器的同步半导体电路。功率管理控制器可操作以将功率施加到其中一个时钟源并选择另一个时钟源以用于该电路的同步。然后，在稳定第一时钟源时，由电源管理控制器选择电路同步。

46. 发明申请

US20090323214A1 Modulated Disk Lock Clock and Methods for Using Such 有权
标题翻译：调制磁盘锁定时钟及使用方法
公开(公告)号：US20090323214A1
公开(公告)日：2009-12-31
申请号：US12147543
申请日：2008-06-27
申请人： Jeffrey P. Grundvig , Richard Rauschmayer
发明人： Jeffrey P. Grundvig , Richard Rauschmayer
IPC分类号： G11B5/09 , G11B15/18
CPC分类号： G11B20/14 , G11B20/10222 , G11B2020/1476 , G11B2020/1484 , G11B2220/2516
摘要： Various embodiments of the present invention provide systems and methods for controlling access to a magnetic storage medium. As one example, a method for controlling access to a storage medium is disclosed that includes calculating a point to point error amount, and generating a incremental error value based at least in part on the point to point error amount. The incremental error value is applied incrementally across a defined number of clock cycles.
摘要翻译：本发明的各种实施例提供了用于控制对磁存储介质的访问的系统和方法。作为一个示例，公开了一种用于控制对存储介质的访问的方法，其包括计算点对点误差量，并且至少部分地基于点对点误差量生成增量误差值。递增错误值在规定数量的时钟周期内逐步应用。

47. 发明授权

US07529320B2 Format efficient timing acquisition for magnetic recording read channels 有权
标题翻译：为磁记录读通道格式化高效的定时采集
公开(公告)号：US07529320B2
公开(公告)日：2009-05-05
申请号：US11228762
申请日：2005-09-16
申请人： Jason Byrne , German Feyh , Jeffrey Grundvig , Aravind Nayak , Richard Rauschmayer
发明人： Jason Byrne , German Feyh , Jeffrey Grundvig , Aravind Nayak , Richard Rauschmayer
IPC分类号： H04L27/00
CPC分类号： H04L7/0054 , H04L7/0004 , H04L2007/047
摘要： A timing recovery circuit for magnetic recording applications that use preamble synchronization bits. The timing recovery circuit uses a modified digital phase lock loop having a digital rotator. An analog to digital converter (ADC) receives an analog input and provides ADC digital samples to the digital rotator. In order to compensate for analog delay and slewing, it is noted that changing the sampling point in the ADC is equivalent to introducing a phase change in the output. This phase change can be introduced much faster digitally, using a digital rotator, for example, than through changing the analog sampling points. The digital rotator snaps to an initial phase estimate almost instantly as compared to the time required to change the ADC sampling points. As the ADC slews to the initial phase estimate, the digital rotator derotates in step until the ADC reaches the initial phase estimate.
摘要翻译：一种使用前置码同步位的磁记录应用的定时恢复电路。定时恢复电路使用具有数字旋转器的经修改的数字锁相环。模数转换器（ADC）接收模拟输入，并向数字旋转器提供ADC数字采样。为了补偿模拟延迟和回转，应注意，改变ADC中的采样点等同于在输出中引入相位变化。例如，使用数字旋转器可以比通过改变模拟采样点更快地数字地引入该相位变化。与改变ADC采样点所需的时间相比，数字旋转器几乎瞬间捕捉到初始相位估计。当ADC转换到初始相位估计时，数字旋转器将逐步退化，直到ADC达到初始相位估计。

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