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1. 发明申请

US20150139376A1 SIGNAL PROPAGATION SYSTEM AND METHOD OF REDUCING ELECTROMAGNETIC RADIATION EMISSIONS CAUSED BY COMMUNICATION OF TIMING INFORMATION 有权
标题翻译：信号传播系统和减少时序信息通信导致的电磁辐射发射的方法
公开(公告)号：US20150139376A1
公开(公告)日：2015-05-21
申请号：US14130048
申请日：2012-07-02
申请人： Jan Johannes Maria Van Den Elzen
发明人： Jan Johannes Maria Van Den Elzen
IPC分类号： H04B15/02 , H04L7/00
CPC分类号： H04B15/02 , H04B2215/064 , H04L7/0008 , H04L7/0012 , H04L7/033 , H04L2007/047
摘要： A signal propagation system for communicating timing information comprises a processing resource (300) arranged to generate a first timing signal for communicating the timing information, the first timing signal having a first frequency spectrum associated therewith. An electronic circuit (110) is provided having an input for receiving the timing information. An electrical connection (310) between the processing resource (300) and the electronic circuit (110) is also provided. A signal transformation module (304) for communicating the timing information, and the signal transformation module (304) is arranged to translate the first timing signal into a second timing signal for communicating the timing information. The second timing signal has a second frequency spectrum associated therewith that comprises fewer harmonics than the first timing signal, thereby reducing electromagnetic energy emitted by the electrical connection.
摘要翻译：用于传送定时信息的信号传播系统包括被配置为产生用于传送定时信息的第一定时信号的处理资源（300），第一定时信号具有与之相关联的第一频谱。提供具有用于接收定时信息的输入的电子电路（110）。还提供了处理资源（300）和电子电路（110）之间的电连接（310）。用于传送定时信息的信号变换模块（304）和信号变换模块（304）被布置成将第一定时信号转换成用于传送定时信息的第二定时信号。第二定时信号具有与其相关联的第二频谱，其包括比第一定时信号更少的谐波，从而减少由电连接发射的电磁能。

2. 发明申请

US20130251083A1 Synchronization Between Devices 有权
标题翻译：设备之间的同步
公开(公告)号：US20130251083A1
公开(公告)日：2013-09-26
申请号：US13889944
申请日：2013-05-08
申请人： SCHLUMBERGER TECHNOLOGY CORPORATION
发明人： Michael Montgomery , Julius Kusuma , Jean Seydoux , Desheng Zhang
IPC分类号： H04L7/00
CPC分类号： G01V11/002 , G01V13/00 , G01V2200/12 , G06F1/12 , H04J3/0638 , H04L7/0054 , H04L7/04 , H04L7/08 , H04L2007/047
摘要： The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.
摘要翻译：本公开涉及当使用单独的时钟时确定时钟信号的方法。在一个实施例中，提供了包括更新子系统和综合子系统的纪律时钟系统。向更新子系统提供第一时钟相位估计，并与更新子系统一起使用以确定频率偏移估计和相位偏移估计。时钟信号是使用频率偏移估计，相位偏移估计和合成子系统来确定的。或者，可以通过产生与第一时钟相关联的信号来同步两个时钟; 调制信号; 发送调制信号; 通过与第二时钟相关联的接收机接收调制信号; 对接收的信号进行相关; 确定接收到的信号的到达时间; 确定两个时钟之间的时差; 并同步两个时钟。

3. 发明申请

US20130106614A9 SYNCHRONIZATION BETWEEN DEVICES 有权
标题翻译：设备之间的同步
公开(公告)号：US20130106614A9
公开(公告)日：2013-05-02
申请号：US12817355
申请日：2010-06-17
申请人： MICHAEL MONTGOMERY , Julius Kusuma , Jean Seydoux , Desheng Zhang
发明人： MICHAEL MONTGOMERY , Julius Kusuma , Jean Seydoux , Desheng Zhang
IPC分类号： G01V3/00 , H04L7/02
CPC分类号： G01V11/002 , G01V13/00 , G01V2200/12 , G06F1/12 , H04J3/0638 , H04L7/0054 , H04L7/04 , H04L7/08 , H04L2007/047
摘要： The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.
摘要翻译：本公开涉及当使用单独的时钟时确定时钟信号的方法。在一个实施例中，提供了包括更新子系统和综合子系统的纪律时钟系统。向更新子系统提供第一时钟相位估计，并与更新子系统一起使用以确定频率偏移估计和相位偏移估计。时钟信号是使用频率偏移估计，相位偏移估计和合成子系统来确定的。或者，可以通过产生与第一时钟相关联的信号来同步两个时钟; 调制信号; 发送调制信号; 通过与第二时钟相关联的接收机接收调制信号; 对接收的信号进行相关; 确定接收到的信号的到达时间; 确定两个时钟之间的时差; 并同步两个时钟。

4. 发明授权

US08155176B2 Digital equalization process and mechanism 有权
标题翻译：数字均衡过程与机制
公开(公告)号：US08155176B2
公开(公告)日：2012-04-10
申请号：US10486243
申请日：2002-08-09
申请人： Michael B. Propp , Khaled Saab
发明人： Michael B. Propp , Khaled Saab
IPC分类号： H03H7/30 , H04L7/00 , H04B15/00
CPC分类号： H03H17/02 , H03H17/0213 , H03H17/0294 , H03H21/0012 , H04B3/145 , H04B3/54 , H04B2203/5425 , H04B2203/5491 , H04L25/03159 , H04L2007/047 , H04L2025/03522
摘要： A filter is created by sampling noise during an inter-frame gap (110) of a received signal, sampling a data frame preamble (115) from within a data frame (105) of the received signal, and computing filter coefficients based on the noise sampled during the inter-frame gap (110) and the data frame preamble (115) sampled from within the data frame (105).
摘要翻译：通过在接收信号的帧间间隙（110）期间采样噪声来创建滤波器，从接收信号的数据帧（105）中对数据帧前导码（115）进行采样，并且基于噪声来计算滤波器系数在帧间间隙（110）和从数据帧（105）内采样的数据帧前导码（115）中采样。

5. 发明申请

US20110309948A1 SYNCHRONIZATION BETWEEN DEVICES 有权
标题翻译：设备之间的同步
公开(公告)号：US20110309948A1
公开(公告)日：2011-12-22
申请号：US12817355
申请日：2010-06-17
申请人： MICHAEL MONTGOMERY , Julius Kusuma , Jean Seydoux , Desheng Zhang
发明人： MICHAEL MONTGOMERY , Julius Kusuma , Jean Seydoux , Desheng Zhang
IPC分类号： G01V3/00 , H04L7/02
CPC分类号： G01V11/002 , G01V13/00 , G01V2200/12 , G06F1/12 , H04J3/0638 , H04L7/0054 , H04L7/04 , H04L7/08 , H04L2007/047
摘要： The present disclosure relates to a method to determine a clock signal when separate clocks are used. In one embodiment, a disciplined clock system comprising an update subsystem and a synthesis subsystem is provided. A first clock phase estimate is provided to the update subsystem and used, along with the update subsystem, to determine a frequency offset estimate and a phase offset estimate. The clock signal is determining using the frequency offset estimate, the phase offset estimate, and the synthesis subsystem. Alternatively, two clocks can be synchronized by generating a signal associated with a first clock; modulating the signal; transmitting the modulated signal; receiving the modulated signal by a receiver associated with a second clock; correlating the received signal; determining the time of arrival of the received signal; determining the time difference between the two clocks; and synchronizing the two clocks.
摘要翻译：本公开涉及当使用单独的时钟时确定时钟信号的方法。在一个实施例中，提供了包括更新子系统和综合子系统的纪律时钟系统。向更新子系统提供第一时钟相位估计，并与更新子系统一起使用以确定频率偏移估计和相位偏移估计。时钟信号是使用频率偏移估计，相位偏移估计和合成子系统来确定的。或者，可以通过产生与第一时钟相关联的信号来同步两个时钟; 调制信号; 发送调制信号; 通过与第二时钟相关联的接收机接收调制信号; 对接收的信号进行相关; 确定接收到的信号的到达时间; 确定两个时钟之间的时差; 并同步两个时钟。

6. 发明授权

US07649568B2 Image data decoding method of image vertical blanking interval and a device thereof 失效
标题翻译：图像垂直消隐间隔的图像数据解码方法及其装置
公开(公告)号：US07649568B2
公开(公告)日：2010-01-19
申请号：US11293746
申请日：2005-12-02
申请人： Yuan-Hao Huang , Chiuan-Shian Chen
发明人： Yuan-Hao Huang , Chiuan-Shian Chen
IPC分类号： H04N7/087 , H03L7/00
CPC分类号： H04N7/0352 , H03M1/0836 , H04L7/0334 , H04L2007/047 , H04N7/035
摘要： An image data decoding method of an image vertical blanking interval (VBI) and device thereof can adjust a run-in clock signal of data lines of teletext to a data phase of teletext data lines. The method can accurately decode data of the teletext data lines to avoid a phase bias and an erroneous decoding result. A main technical method to decode the data of the VBI is to extract the data of the teletext data lines to determine corresponding bit logical values of the image data and then to output a decode result and also output a phase adjustment value. The phase adjustment value is used to adjust a read phase value of the extracted image so as to synchronize a data phase in VBI.
摘要翻译：图像垂直消隐间隔（VBI）的图像数据解码方法及其装置可以将图文数据线的输入时钟信号调整到图文电视数据线的数据相位。该方法可以准确地解码图文数据线的数据，以避免相位偏差和错误解码结果。用于对VBI的数据进行解码的主要技术方法是提取图文数据线的数据，以确定图像数据的对应位逻辑值，然后输出解码结果，并输出相位调整值。相位调整值用于调整提取的图像的读取相位值，以使VBI中的数据相位同步。

7. 发明授权

US07519750B2 Linear burst mode synchronizer for passive optical networks 有权
标题翻译：无源光网络的线性突发模式同步器
公开(公告)号：US07519750B2
公开(公告)日：2009-04-14
申请号：US11488124
申请日：2006-07-18
申请人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
发明人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
IPC分类号： G06F13/00 , G06F13/42 , G06F12/00 , H03L7/06 , H03K5/01
CPC分类号： H04L7/10 , H03L7/0807 , H03L7/087 , H04L7/033 , H04L2007/047
摘要： The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要翻译：本发明公开了一种用于无源光网络的主机接收机同步器，特别是具有小于250ns的非数据前导码的突发异步通信系统中的主机接收机中的突发时钟数据恢复电路，用于从订户数据突发。该电路包括：可调节振荡器，用于响应于其输入端的信号产生输出时钟信号; 第一比较器，用于将输出时钟信号的频率和相位与参考信号的频率和相位进行比较，并将第一反馈信号反馈到振荡器输入; 以及第二比较器，用于在输出时钟信号与参考信号锁定频率时，将输出时钟信号的频率和相位与数据脉冲串的频率和相位进行比较，并将第二反馈信号反馈到振荡器输入。在接收到前同步码的最后一位之前，输出时钟信号被锁定在数据脉冲串的频率和相位上。本发明的优点在于接收机电路提高了现有技术解决方案的同步抖动性能，从而提供额外的时序余量，从而允许支持更长的光纤长度。

8. 发明申请

US20080022143A1 Linear burst mode synchronizer for passive optical networks 有权
标题翻译：无源光网络的线性突发模式同步器
公开(公告)号：US20080022143A1
公开(公告)日：2008-01-24
申请号：US11488124
申请日：2006-07-18
申请人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
发明人： Shawn Scouten , Colin Cramm , Malcolm Stevens , Kenji Suzuki , Brian Wall , Med Belhadj
IPC分类号： G06F1/12
CPC分类号： H04L7/10 , H03L7/0807 , H03L7/087 , H04L7/033 , H04L2007/047
摘要： The present invention discloses a host receiver synchronizer for passive optical networks, and in particular a burst clock data recovery circuit in a host receiver in a bursty asynchronous communication system having a non-data preamble of less than 250 ns, for recovering a clock signal from a subscriber data burst. The circuit comprises: an adjustable oscillator for generating an output clock signal in response to a signal at an input thereof; a first comparator for comparing a frequency and phase of the output clock signal to that of a reference signal and feeding back a first feedback signal to the oscillator input; and a second comparator for comparing the frequency and phase of the output clock signal to that of the data burst and feeding back a second feedback signal to the oscillator input once the output clock signal is locked in frequency with the reference signal. The output clock signal is locked in frequency and phase to the data burst before receipt of the last bit of the preamble. The present invention is advantageous in that the receiver circuit improves synchronized jitter performance over the prior art solutions so that additional timing margin is provided, thereby allowing longer fiber lengths to be supported.
摘要翻译：本发明公开了一种用于无源光网络的主机接收机同步器，特别是具有小于250ns的非数据前导码的突发异步通信系统中的主机接收机中的突发时钟数据恢复电路，用于从订户数据突发。该电路包括：可调节振荡器，用于响应于其输入端的信号产生输出时钟信号; 第一比较器，用于将输出时钟信号的频率和相位与参考信号的频率和相位进行比较，并将第一反馈信号反馈到振荡器输入; 以及第二比较器，用于在输出时钟信号与参考信号锁定频率时，将输出时钟信号的频率和相位与数据脉冲串的频率和相位进行比较，并将第二反馈信号反馈到振荡器输入。在接收到前同步码的最后一位之前，输出时钟信号被锁定在数据脉冲串的频率和相位上。本发明的优点在于接收机电路提高了现有技术解决方案的同步抖动性能，从而提供额外的时序余量，从而允许支持更长的光纤长度。

9. 发明申请

US20070121189A1 DATA TRANSMISSION DEVICES FOR COMMUNICATION FACILITIES OF A PASSIVE OPTICAL NETWORK 审中-公开
标题翻译：用于被动光网络通信设备的数据传输设备
公开(公告)号：US20070121189A1
公开(公告)日：2007-05-31
申请号：US11560360
申请日：2006-11-16
申请人： Thierry ZAMI , Dominique Chiaroni
发明人： Thierry ZAMI , Dominique Chiaroni
IPC分类号： G02F1/03 , G02F1/07
CPC分类号： H04B10/2587 , H04B10/27 , H04B10/272 , H04L7/0075 , H04L7/08 , H04L2007/047
摘要： A passive optical network comprises at least one communication facility, termed network head, coupled to at least two communication facilities, termed remote, by transmission and routing means. The network head is charged with transmitting to the remote facilities an alternation of a first portion of an optical carrier, modulated by data to be transmitted according to a chosen bit rate and lasting a first time interval, and of a second portion of this optical carrier, modulated by a clock signal at a base frequency corresponding to the bit rate and lasting a second time interval. Each remote facility is charged, on the one hand, with recovering the base frequency in the first and second received portions, and, on the other hand, with transmitting to the network head, during chosen time slots synchronized by the network head, the part which corresponds to these time slots in some at least of the second portions received successively after having overmodulated with data to be transmitted the clock signal that it contains.
摘要翻译：无源光网络包括被称为网络头的至少一个通信设施，通过传输和路由装置耦合到称为远程的至少两个通信设施。网络头被充电以向远程设施发送光载波的第一部分的交替，由根据选择的比特率并持续第一时间间隔的将被发送的数据调制，以及该光载波的第二部分，由与比特率对应的基本频率的时钟信号调制，并持续第二时间间隔。一方面，每个远程设施对第一和第二接收部分恢复基本频率进行充电，另一方面，在由网络头同步的所选择的时隙期间，向网络头发送，部分其对应于在具有要被发送的数据被过度调制的至少第二部分中的这些时隙中，所述数据被包含在其中。

10. 发明授权

US07203254B2 Method and system for synchronizing in a frequency shift keying receiver 有权
标题翻译：用于在频移键控接收机中同步的方法和系统
公开(公告)号：US07203254B2
公开(公告)日：2007-04-10
申请号：US10397027
申请日：2003-03-25
申请人： Stephen R. Carsello , Mark A. Goldberg
发明人： Stephen R. Carsello , Mark A. Goldberg
IPC分类号： H04L27/14 , H03D3/00
CPC分类号： H04L7/042 , H04L7/08 , H04L27/10 , H04L2007/047 , H04L2027/0065 , H04L2027/0095
摘要： The invention provides a method and apparatus for achieving timing synchronization during signal acquisition and for achieving frequency synchronization in a digital communication receiver after signal acquisition. The invention operates by performing multiple correlations of a received signal, each correlation performed over an symbol interval and correlating the received signal in the symbol interval with a sinusoid of an expected frequency. The correlations are combined to determine a peak and energy, and if the peak to energy ratio is above a threshold, the symbol timing and frequency offset is estimated.
摘要翻译：本发明提供一种用于在信号采集期间实现定时同步并在信号采集之后实现数字通信接收机中的频率同步的方法和装置。本发明通过执行接收信号的多个相关性进行操作，每个相关性在符号间隔上执行，并将符号间隔中的接收信号与期望频率的正弦相关。相关性被组合以确定峰值和能量，并且如果峰值与能量比高于阈值，则估计符号定时和频率偏移。

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