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41. 发明授权

US07027326B2 3T1D memory cells using gated diodes and methods of use thereof 失效
标题翻译： 3T1D存储单元，使用门控二极管及其使用方法
公开(公告)号：US07027326B2
公开(公告)日：2006-04-11
申请号：US10751713
申请日：2004-01-05
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： G11C11/36 , G11C11/24 , G11C8/16
CPC分类号： H01L27/108 , G11C11/405 , H01L27/1021 , H01L29/7391
摘要： A memory cell comprises: (1) a write switch, the first terminal of the write switch coupled to an at least one bitline, the control terminal of the write switch coupled to the first control line; (2) a two terminal semiconductor, the first terminal of the two terminal semiconductor device coupled to the second terminal of the write switch, and the second terminal of the two terminal semiconductor device coupled to an at least one second control line, wherein the two terminal semiconductor device has a capacitance when a voltage on the first terminal relative to the second terminal is above a threshold voltage and has a lower capacitance when the voltage on the first terminal relative to the second terminal is less than the threshold voltage; (3) a read select switch, the control terminal of the read select switch coupled to an at least one second control line, the first terminal of the read select switch coupled to the at least one bitline; and (4) a read switch, the control terminal of the read switch coupled to the first terminal of the gated diode and coupled to the second terminal of the write switch, the first terminal of the read switch coupled to the second terminal of the read select gate, and the second terminal of the read switch coupled to ground.
摘要翻译：存储器单元包括：（1）写开关，写开关的第一端耦合到至少一个位线，写开关的控制端耦合到第一控制线; （2）二端子半导体，耦合到写开关的第二端的两端子半导体器件的第一端子和耦合到至少一个第二控制线的两端子半导体器件的第二端子，其中两当所述第一端子上的电压相对于所述第二端子的电压高于阈值电压并且当所述第一端子上的相对于所述第二端子的电压小于所述阈值电压时，所述端子半导体器件具有较小的电容; （3）读选择开关，所述读选择开关的控制端耦合到至少一个第二控制线，所述读选择开关的第一端耦合到所述至少一位线; 和（4）读取开关，读取开关的控制端子耦合到门控二极管的第一端子并耦合到写入开关的第二端子，读取开关的第一端子耦合到读取的第二端子选择门，读取开关的第二个端子耦合到地。

42. 发明授权

US06982897B2 Nondestructive read, two-switch, single-charge-storage device RAM devices 失效
标题翻译：无损读取，双开关，单电荷存储器件RAM器件
公开(公告)号：US06982897B2
公开(公告)日：2006-01-03
申请号：US10680348
申请日：2003-10-07
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： G11C11/24
CPC分类号： H01L27/108 , G11C11/405
摘要： A random access memory (RAM) circuit is coupled to a write control line, a read control line, and one or more bitlines, and includes a write switch having a control terminal and first and second terminals. The first terminal of the write switch is coupled to the one or more bitlines, and the control terminal of the write switch is coupled to the write control line. The circuit includes a charge-storage device having first and second terminals, wherein a first terminal of the charge-storage device is coupled to the second terminal of the write switch and a second terminal of the charge-storage device is coupled to the read control line. The circuit includes a read switch having a control terminal and first and second terminals. The control terminal of the read switch is coupled to the first terminal of the charge-storage device and is coupled to the second terminal of the write switch. The first terminal of the read switch is coupled to the one or more bitlines, and the second terminal of the read switch coupled to ground. The circuit may be implemented through a number of disclosed semiconductor memory devices.
摘要翻译：随机存取存储器（RAM）电路耦合到写入控制线，读取控制线和一个或多个位线，并且包括具有控制端子和第一和第二端子的写入开关。写开关的第一端耦合到一个或多个位线，并且写开关的控制端耦合到写控制线。该电路包括具有第一和第二端子的电荷存储装置，其中电荷存储装置的第一端子耦合到写入开关的第二端子，并且电荷存储装置的第二端子耦合到读取控制线。电路包括具有控制端子和第一和第二端子的读取开关。读开关的控制端耦合到电荷存储装置的第一端并耦合到写开关的第二端。读开关的第一端耦合到一个或多个位线，并且读开关的第二端耦合到地。电路可以通过许多公开的半导体存储器件实现。

43. 发明授权

US06426905B1 High speed DRAM local bit line sense amplifier 失效
标题翻译：高速DRAM本地位线读出放大器
公开(公告)号：US06426905B1
公开(公告)日：2002-07-30
申请号：US09777004
申请日：2001-02-07
申请人： Robert H. Dennard , Ronald W. Knepper
发明人： Robert H. Dennard , Ronald W. Knepper
IPC分类号： G11C700
CPC分类号： G11C7/062 , G11C7/10 , G11C7/1051 , G11C11/4091
摘要： Disclosed is a high speed sense amplifier circuit designed for sensing data in one-transistor DRAM memory cells on bit lines within DRAM macros. The circuit utilizes a charge transfer scheme to rapidly remove charge from a small sensing first capacitor C1, generating a voltage swing delta V1, via an FET operating in its subthreshold region by means of idling current, such transfer supplying an equal charge to the larger bit line capacitance Cb1 with small voltage swing delta Vb1. The sense amp is pre-charged to the “1” state, and senses a “0” via the charge transfer operation thusly described. A “1” is sensed when no charge transfer takes place.
摘要翻译：公开了一种设计用于在DRAM宏内的位线上感测单晶体管DRAM存储单元中的数据的高速感测放大器电路。该电路利用电荷转移方案从小的感测第一电容器C1快速去除电荷，通过借助于空载电流在其亚阈值区域中工作的FET产生电压摆幅增量V1，这种转移为较大的位提供相等的电荷具有小电压摆幅增量Vb1的线电容Cb1。感测放大器被预充电到“1”状态，并且通过如上所述的电荷转移操作来感测“0”。当不发生电荷转移时，感测到“1”。

44. 发明授权

US5378943A Low power interface circuit 失效
公开(公告)号：US5378943A
公开(公告)日：1995-01-03
申请号：US49912
申请日：1993-04-20
申请人： Robert H. Dennard
发明人： Robert H. Dennard
IPC分类号： H03K5/02 , G11C11/407 , G11C11/409 , H03K19/00 , H03K19/0185 , H03K19/094
CPC分类号： H03K19/018521 , H03K19/0013
摘要： The interface circuit of the present invention adjusts the signal voltage across a leaking transistor such that the leakage is reduced while also shunting out the adjustment means when the adjustment means impedes the operation of the interface circuit. One embodiment of the present invention is a level translator comprised of a level shifting stage coupled to a buffer stage. The level shifting stage has its power source coupled to a current shunting device. The current shunting device is connected in parallel across the first P-channel device of the level shifting stage. The first P-channel device of the level shifting stage is connected in series with a second P-channel device having its drain connected to a drain of a first N-channel device wherein the first N-channel device has its source connected to a drain of a second N-channel device. The current shunting device is formed from a single P-channel device. The connection between the drains of the second P-channel and the first N-channel device of the level shifting stage is an input to an inverter, which in turn, has its output connected to the input of the current shunting device. When the input to the level shift stage is at the high voltage logic signal level, the input to the inverter is low and the output of the inverter is at a high voltage logic signal level. The high voltage logic signal level then turns off the P-channel device of the current shunting device. The first P-channel device of the level shifting stage has its gate connected to its drain which reduces leakage current in the level shifting stage and reduces the power consumed by the interface circuit when the current shunting device is turned off. When the input to the level shift stage is at the low voltage logic signal level, the input to the inverter is high and the output of the inverter is at a low voltage logic signal level. The low voltage logic signal level allows the current shunting device to directly supply current to the second P-channel device of the level shifting stage and shunts out the first P-channel device. Therefore, the shunted out device does not interfere with the performance of the level shift stage of the interface circuit.

45. 发明授权

US4160987A Field effect transistors with polycrystalline silicon gate self-aligned to both conductive and non-conductive regions and fabrication of integrated circuits containing the transistors 失效
标题翻译：具有与导电和非导电区域自对准的多晶硅栅极的场效应晶体管以及包含晶体管的集成电路的制造
公开(公告)号：US4160987A
公开(公告)日：1979-07-10
申请号：US804200
申请日：1977-06-06
申请人： Robert H. Dennard , Vincent L. Rideout
发明人： Robert H. Dennard , Vincent L. Rideout
IPC分类号： H01L27/10 , H01L21/28 , H01L21/316 , H01L21/336 , H01L21/762 , H01L21/8242 , H01L23/522 , H01L27/108 , H01L29/06 , H01L29/423 , H01L29/49 , H01L29/78 , H01L27/02
CPC分类号： H01L29/78 , H01L21/28123 , H01L21/76202 , H01L23/522 , H01L27/10805 , H01L29/0638 , H01L29/4232 , H01L29/4238 , H01L29/4925 , H01L29/4983 , H01L29/66575 , H01L2924/0002 , Y10S148/053 , Y10S148/103 , Y10S148/106 , Y10S148/117 , Y10S148/141 , Y10S148/147
摘要： A field effect transistor (FET) with a unique gate structure is disclosed wherein the polycrystalline silicon (polysilicon) gate is self-aligned on its ends with respect to the conductive source and drain regions, and is self-aligned on its sides with respect to the nonconductive field isolation regions. The boundaries of these conductive and nonconductive regions determine the boundaries of the channel region of the FET. This double self-alignment feature results in a polysilicon gate, the lateral dimensions and location of which correlate directly with the lateral dimensions and location of the channel region of the FET. The unique gate fabrication technique employed according to the present invention comprises delineating lithographic patterns twice in the same polysilicon layer using the same oxidation barrier masking layer; whereby the first lithographic pattern delineates the FET device regions, and the next lithographic pattern forms the gate regions wherever the two patterns cross each other (i.e., wherever they delineate a common area).
摘要翻译：公开了具有唯一栅极结构的场效应晶体管（FET），其中多晶硅（多晶硅）栅极在其端部上相对于导电源极和漏极区域自对准，并且在其侧面上相对于非导电场隔离区。这些导电和非导电区域的边界决定了FET的沟道区域的边界。该双重自对准特征导致多晶硅栅极，其横向尺寸和位置直接与FET的沟道区域的横向尺寸和位置相关。根据本发明采用的唯一栅极制造技术包括使用相同的氧化屏障掩蔽层在同一多晶硅层中描绘两次光刻图案; 由此第一平版印刷图案描绘了FET器件区域，并且下一个光刻图案形成了两个图案彼此交叉（即，它们划定公共区域的任何地方）的栅极区域。

46. 发明申请

US20130196483A1 SOI STRUCTURES INCLUDING A BURIED BORON NITRIDE DIELECTRIC 审中-公开
标题翻译： SOI结构包括一个BURIED BORON NITRIDE DIELECTRIC
公开(公告)号：US20130196483A1
公开(公告)日：2013-08-01
申请号：US13604004
申请日：2012-09-05
申请人： Robert H. Dennard , Alfred Grill , Effendi Leobandung , Deborah A. Neumayer , Dea-Gyu Park , Ghavam G. Shahidi , Leathen Shi
发明人： Robert H. Dennard , Alfred Grill , Effendi Leobandung , Deborah A. Neumayer , Dea-Gyu Park , Ghavam G. Shahidi , Leathen Shi
IPC分类号： H01L21/30
CPC分类号： H01L29/78603 , H01L21/02112 , H01L21/02274 , H01L21/0228 , H01L21/76254
摘要： Boron nitride is used as a buried dielectric of an SOI structure including an SOI layer and a handle substrate. The boron nitride is located between an SOI layer and a handle substrate. Boron nitride has a dielectric constant and a thermal expansion coefficient close to silicon dioxide. Yet, boron nitride has a wet as well as a dry etch resistance that is much better than silicon dioxide. In the SOI structure, there is a reduced material loss of boron nitride during multiple wet and dry etches so that the topography and/or bridging are not an obstacle for device integration. Boron nitride has a low dielectric constant so that devices built in SOI active regions do not suffer from a charging effect.
摘要翻译：氮化硼被用作包括SOI层和手柄衬底的SOI结构的掩埋电介质。氮化硼位于SOI层和手柄基板之间。氮化硼具有接近二氧化硅的介电常数和热膨胀系数。然而，氮化硼具有比二氧化硅好得多的湿润以及耐干蚀刻性。在SOI结构中，在多次湿和干蚀刻期间氮化硼的材料损失减少，使得形貌和/或桥接不是器件集成的障碍。氮化硼具有低介电常数，使得内置在SOI有源区中的器件不会带来充电效应。

47. 发明申请

US20130057347A1 AMPLIFIERS USING GATED DIODES 有权
标题翻译：使用栅极二极管的放大器
公开(公告)号：US20130057347A1
公开(公告)日：2013-03-07
申请号：US13604995
申请日：2012-09-06
申请人： Wing K. Luk , Robert H. Dennard
发明人： Wing K. Luk , Robert H. Dennard
IPC分类号： H03G3/00
CPC分类号： H03F1/56 , G11C7/06 , H01L27/0811 , H01L29/7391 , H03F2200/183
摘要： A circuit comprises a control line and a two terminal semiconductor device having a first terminal is coupled to a signal line, and a second terminal is coupled to the control line. The semiconductor device has a capacitance when a voltage on the first terminal is above a threshold and has a smaller capacitance when a voltage on the first terminal is below the threshold. A signal is placed on the signal line and a voltage on the control line is modified. When the signal falls below the threshold, the semiconductor device acts as a very small capacitor and the output will be a small value. When the signal is above the threshold, the semiconductor device acts as a large capacitor and the output will be influenced by the signal and the modified voltage on the control line and the signal is amplified.
摘要翻译：电路包括控制线和具有第一端子的两端子半导体器件耦合到信号线，并且第二端子耦合到控制线。当第一端子上的电压高于阈值时，半导体器件具有电容，并且当第一端子上的电压低于阈值时具有较小的电容。信号被置于信号线上，控制线上的电压被改变。当信号低于阈值时，半导体器件充当非常小的电容器，并且输出将是小的值。当信号高于阈值时，半导体器件用作大电容器，输出将受到信号和控制线上修改的电压的影响，信号被放大。

48. 发明申请

US20130015912A1 SOI CMOS STRUCTURE HAVING PROGRAMMABLE FLOATING BACKPLATE 审中-公开
标题翻译：具有可编程浮动背板的SOI CMOS结构
公开(公告)号：US20130015912A1
公开(公告)日：2013-01-17
申请号：US13612036
申请日：2012-09-12
申请人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
发明人： Jin Cai , Robert H. Dennard , Ali Khakifirooz , Tak H. Ning , Jeng-Bang Yau
IPC分类号： G05F3/02
CPC分类号： H01L21/84 , H01L27/1203 , H01L29/7841
摘要： SOI CMOS structures having at least one programmable electrically floating backplate are provided. Each electrically floating backplate is individually programmable. Programming can be performed by injecting electrons into each conductive floating backplate. Erasure of the programming can be accomplished by tunneling the electrons out of the floating backplate. At least one of two means can accomplish programming of the electrically floating backgate. The two means include Fowler-Nordheim tunneling, and hot electron injection using an SOI pFET. Hot electron injection using pFET can be done at much lower voltage than injection by tunneling electron injection.
摘要翻译：提供具有至少一个可编程电浮动背板的SOI CMOS结构。每个电浮动背板均可单独编程。可以通过将电子注入每个导电浮动背板来进行编程。编程的擦除可以通过将电子穿过浮动背板来实现。两个装置中的至少一个可以完成电浮动背栅的编程。这两种方法包括Fowler-Nordheim隧道和使用SOI pFET的热电子注入。使用pFET的热电子注入可以通过隧道电子注入在比注入低得多的电压下进行。

49. 发明申请

US20120262226A1 SWITCHED CAPACITOR VOLTAGE CONVERTERS 有权
标题翻译：开关电容电压转换器
公开(公告)号：US20120262226A1
公开(公告)日：2012-10-18
申请号：US13532986
申请日：2012-06-26
申请人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
发明人： Robert H. Dennard , Brian L. Ji , Robert K. Montoye
IPC分类号： G05F1/10
CPC分类号： G11C5/145 , H02M3/07
摘要： An on-chip voltage conversion apparatus for integrated circuits includes a first capacitor; a first NFET device configured to selectively couple a first electrode of the first capacitor to a low side voltage rail of a first voltage domain; a first PFET device configured to selectively couple the first electrode of the first capacitor to a high side voltage rail of the first voltage domain; a second NFET device configured to selectively couple a second electrode of the first capacitor to a low side voltage rail of a second voltage domain, wherein the low side voltage rail of the second voltage domain corresponds to the high side voltage rail of the first voltage domain; and a second PFET device configured to selectively couple the second electrode of the first capacitor to a high side voltage rail of the second voltage domain.
摘要翻译：集成电路的片上电压转换装置包括第一电容器; 第一NFET器件被配置为选择性地将第一电容器的第一电极耦合到第一电压域的低侧电压轨; 第一PFET器件，被配置为选择性地将第一电容器的第一电极耦合到第一电压域的高侧电压轨; 第二NFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的低侧电压轨，其中第二电压域的低侧电压轨对应于第一电压域的高侧电压轨 ; 以及第二PFET器件，被配置为选择性地将第一电容器的第二电极耦合到第二电压域的高侧电压轨。

50. 发明申请

US20120217561A1 Structure And Method For Adjusting Threshold Voltage Of The Array Of Transistors 有权
标题翻译：用于调整晶体管阵列的阈值电压的结构和方法
公开(公告)号：US20120217561A1
公开(公告)日：2012-08-30
申请号：US13036243
申请日：2011-02-28
申请人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
发明人： Ali Khakifirooz , Jin Cai , Kangguo Cheng , Robert H. Dennard , Tak H. Ning
IPC分类号： H01L29/78 , H01L21/66
CPC分类号： G11C11/418 , G11C11/412 , G11C11/419 , G11C29/50004 , G11C2029/5004 , G11C2029/5006 , H01L21/84 , H01L27/11 , H01L27/1104 , H01L27/1108 , H01L27/11568 , H01L27/1203 , H01L29/0603 , H01L29/66833 , H01L29/786 , H01L29/792
摘要： A semiconductor device including a charge storage element present in a buried dielectric layer of the substrate on which the semiconductor device is formed. Charge injection may be used to introduce charge to the charge storage element of the buried dielectric layer that is present within the substrate. The charge that is injected to the charge storage element may be used to adjust the threshold voltage (Vt) of each of the semiconductor devices within an array of semiconductor devices that are present on the substrate.
摘要翻译：一种半导体器件，包括存在于其上形成半导体器件的衬底的埋置介质层中的电荷存储元件。可以使用电荷注入来将电荷引入存在于衬底内的掩埋介电层的电荷存储元件。注入电荷存储元件的电荷可用于调整存在于基板上的半导体器件阵列内的每个半导体器件的阈值电压（Vt）。

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