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    • 5. 发明授权
    • Semiconductor memory
    • 半导体存储器
    • US06829192B2
    • 2004-12-07
    • US10335949
    • 2003-01-03
    • Naoharu ShinozakiYasurou Matsuzaki
    • Naoharu ShinozakiYasurou Matsuzaki
    • G11C700
    • G11C11/40607G11C7/08G11C8/18G11C11/406G11C11/40615G11C11/40622G11C11/4074G11C11/4085G11C11/4091G11C2207/2227G11C2211/4067G11C2211/4068
    • A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.
    • 在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。 操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元,以执行读操作和写操作。 操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。 这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。 由于可以在不进行刷新操作的情况下保持数据,因此可以在低功耗模式下降低功耗。