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1. 发明授权

US06831871B2 Stable memory cell read 失效
公开(公告)号：US06831871B2
公开(公告)日：2004-12-14
申请号：US10334456
申请日：2002-12-30
申请人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De
发明人： Muhammad M. Khellah , Dinesh Somasekhar , Yibin Ye , Vivek K. De
IPC分类号： G11C700
CPC分类号： G11C7/12 , G11C2207/2281
摘要： According to some embodiments, provided are a memory cell, a bit-line coupled to the memory cell, a pre-charge circuit coupled to the bit-line to pre-charge the bit-line, and a discharge device coupled to the bit-line to discharge the bit-line prior to a read of the memory cell.

2. 发明授权

US06831869B2 Semiconductor memory device and electronic information device using the same 失效
标题翻译：半导体存储器件和使用其的电子信息器件
公开(公告)号：US06831869B2
公开(公告)日：2004-12-14
申请号：US10355344
申请日：2003-01-31
申请人： Kaname Yamano
发明人： Kaname Yamano
IPC分类号： G11C700
CPC分类号： G11C29/84 , G11C29/842
摘要： In a semiconductor memory device, a redundant memory cell is accessible based on an input address signal by a redundant word line selection signal which is output in accordance with whether data read is to be performed or a memory operation other than data read is to be performed.
摘要翻译：在半导体存储器件中，冗余存储器单元可以通过根据是否要执行数据读取而输出的冗余字线选择信号的输入地址信号进行访问，还是要执行数据读取以外的存储器操作。

3. 发明授权

US06831866B1 Method and apparatus for read bitline clamping for gain cell DRAM devices 有权
标题翻译：用于增益单元DRAM器件读取位线钳位的方法和装置
公开(公告)号：US06831866B1
公开(公告)日：2004-12-14
申请号：US10604911
申请日：2003-08-26
申请人： Toshiaki K. Kirihata
发明人： Toshiaki K. Kirihata
IPC分类号： G11C700
CPC分类号： G11C11/405 , G11C7/12 , G11C7/14 , G11C11/4094 , G11C11/4099
摘要： A dynamic random access memory (DRAM) storage device includes a storage cell having a plurality of transistors arranged in a gain cell configuration, the gain cell coupled to a read bitline and a write bitline. A dummy cell is configured as a clamping device for the read bitline, wherein the dummy cell opposes a read bitline voltage swing during a read operation of the storage cell.
摘要翻译：动态随机存取存储器（DRAM）存储器件包括具有以增益单元配置排列的多个晶体管的存储单元，所述增益单元耦合到读位线和写位线。虚拟单元被配置为用于读取位线的钳位装置，其中该虚拟单元在存储单元的读取操作期间与读取的位线电压摆动相对。

4. 发明授权

US06831861B2 Methods and memory structures using tunnel-junction device as control element 失效
公开(公告)号：US06831861B2
公开(公告)日：2004-12-14
申请号：US10756450
申请日：2004-01-12
申请人： Peter Fricke , Andrew L. Van Brocklin , James E. Ellenson
发明人： Peter Fricke , Andrew L. Van Brocklin , James E. Ellenson
IPC分类号： G11C700
CPC分类号： G11C13/003 , G11C17/16 , G11C17/18 , G11C2213/76
摘要： A memory structure includes a memory storage element electrically coupled to a control element. The control element comprises a tunnel-junction device. The memory storage element may also comprise a tunnel-junction device. Methods for fusing a tunnel-junction device of a memory storage element without fusing a tunnel-junction device of an associated control element are disclosed. The memory storage element may have an effective cross-sectional area that is greater than an effective cross-sectional area of the control element. A memory structure comprises a memory storage element, a control element comprising a tunnel-junction device electrically coupled to the memory storage element and configured to control the state of the memory storage element, and a reference element. The reference element is configured as a reference to protect the control element when selectively controlling the state of the memory storage element. The reference element may comprise a tunnel-junction device and be used with a current source to fuse a memory storage element without fusing a tunnel-junction device of an associated control element. Methods of making the memory structure and using it in electronic devices are disclosed.

5. 发明授权

US06829192B2 Semiconductor memory 失效
标题翻译：半导体存储器
公开(公告)号：US06829192B2
公开(公告)日：2004-12-07
申请号：US10335949
申请日：2003-01-03
申请人： Naoharu Shinozaki , Yasurou Matsuzaki
发明人： Naoharu Shinozaki , Yasurou Matsuzaki
IPC分类号： G11C700
CPC分类号： G11C11/40607 , G11C7/08 , G11C8/18 , G11C11/406 , G11C11/40615 , G11C11/40622 , G11C11/4074 , G11C11/4085 , G11C11/4091 , G11C2207/2227 , G11C2211/4067 , G11C2211/4068
摘要： A partial area for retaining data during low power consumption mode is composed of a single first memory cell out of a plurality of memory cells connected to a bit line. An operation control circuit operates any of the memory cells selected in accordance with an address signal during normal operation mode for performing a read operation and a write operation. The operation control circuit keeps latching data retained by the first memory cell in the partial area into a sense amplifier during the low power consumption mode. This eliminates the need for a refresh operation for retaining the data in the first memory cell during the low power consumption mode. Since the data can be retained without a refresh operation, it is possible to reduce the power consumption during the low power consumption mode.
摘要翻译：在低功耗模式期间用于保留数据的部分区域由连接到位线的多个存储单元中的单个第一存储单元组成。操作控制电路在正常操作模式期间操作根据地址信号选择的任何存储单元，以执行读操作和写操作。操作控制电路在低功耗模式期间将由部分区域中的第一存储单元保留的数据保持为读出放大器。这消除了在低功耗模式期间需要用于将数据保持在第一存储单元中的刷新操作。由于可以在不进行刷新操作的情况下保持数据，因此可以在低功耗模式下降低功耗。

6. 发明授权

US06829191B1 Magnetic memory equipped with a read control circuit and an output control circuit 有权
标题翻译：磁记忆体配有读控制电路和输出控制电路
公开(公告)号：US06829191B1
公开(公告)日：2004-12-07
申请号：US10726393
申请日：2003-12-03
申请人： Frederick A. Perner , Kenneth Kay Smith , Sarah Morris Brandenberger
发明人： Frederick A. Perner , Kenneth Kay Smith , Sarah Morris Brandenberger
IPC分类号： G11C700
CPC分类号： G11C11/16
摘要： A magnetic memory is disclosed. In one embodiment, the magnetic memory includes first and second memory cells and a read controller coupled to the first and second memory cells. An output controller coupled to the read controller and to the first and second memory cells, wherein the output controller is configured to receive read data in parallel only from the first or second memory cells which have completed the current read operation regardless of whether both the first and second memory cells have completed the current read operation and convert the parallel data to serial data and shift the parallel data to an output in synchronism with the system clock signal.
摘要翻译：公开了磁存储器。在一个实施例中，磁存储器包括耦合到第一和第二存储器单元的第一和第二存储器单元和读取控制器。耦合到读控制器和第一和第二存储器单元的输出控制器，其中输出控制器被配置为仅从已完成当前读操作的第一或第二存储器单元并行地接收读数据，而不管第一并且第二存储单元已经完成当前的读取操作，并且将并行数据转换成串行数据，并且将并行数据与系统时钟信号同步地移位到输出端。

7. 发明授权

US06829178B2 Nonvolatile memory device 失效
标题翻译：非易失性存储器件
公开(公告)号：US06829178B2
公开(公告)日：2004-12-07
申请号：US10269971
申请日：2002-10-15
申请人： Hiyori Koyama , Kazuyoshi Oshima , Akihiko Hoshida , Kiichi Manita , Michitaro Kanamitsu , Shinji Udo , Kazue Kikuchi , Kazuaki Ujiie , Masahiro Sakai
发明人： Hiyori Koyama , Kazuyoshi Oshima , Akihiko Hoshida , Kiichi Manita , Michitaro Kanamitsu , Shinji Udo , Kazue Kikuchi , Kazuaki Ujiie , Masahiro Sakai
IPC分类号： G11C700
CPC分类号： G11C16/3436 , G11C16/04 , G11C29/44
摘要： A counter circuit for counting the number of fails generated during the write and erase processes executed in the predetermined unit such as a sector and a comparison circuit for judging whether the value counted with the counter circuit has exceeded or not the preset allowable value for the number of fails are provided. Accordingly, when the counted value of the counter circuit has exceeded the allowable value set to a register, the write process or erase process is not performed even when a write or erase command is inputted from an external circuit. Thereby, the required test time can be shortened for the electrically programmable and erasable nonvolatile semiconductor memory device such as a flash memory.
摘要翻译：一种用于计数在诸如扇区的预定单元中执行的写入和擦除处理期间产生的失败次数的计数器电路和用于判断由计数器电路计数的值是否超过了数字的预设容许值的比较电路提供失败。因此，当计数器电路的计数值已经超过设置给寄存器的容许值时，即使从外部电路输入写入或擦除命令，也不执行写入处理或擦除处理。因此，对于诸如闪存的电可编程和可擦除的非易失性半导体存储器件，可以缩短所需的测试时间。

8. 发明授权

US06829174B2 Method of narrowing threshold voltage distribution 有权
标题翻译：缩小阈值电压分布的方法
公开(公告)号：US06829174B2
公开(公告)日：2004-12-07
申请号：US10248572
申请日：2003-01-30
申请人： Yao-Wen Chang , Tao-Cheng Lu
发明人： Yao-Wen Chang , Tao-Cheng Lu
IPC分类号： G11C700
CPC分类号： G11C16/16 , G11C16/10
摘要： A method of narrowing the threshold voltage distribution in a memory. The method includes separating the erase and erase identification of odd memory cells from the erase and erase identification of even memory cells in an advanced non-volatile memory so that the distribution of the threshold voltage is narrowed.
摘要翻译：缩小存储器中的阈值电压分布的方法。该方法包括将奇数存储器单元的擦除和擦除识别与高级非易失性存储器中的偶数存储器单元的擦除和擦除识别分离，使得阈值电压的分布变窄。

9. 发明授权

US06826109B2 Semiconductor integrated circuit device with a RAM macro having two operation modes for receiving an input signal at different timings 失效
标题翻译：具有RAM宏的半导体集成电路装置具有两种操作模式，用于在不同的定时接收输入信号
公开(公告)号：US06826109B2
公开(公告)日：2004-11-30
申请号：US10345186
申请日：2003-01-16
申请人： Shigeru Nakahara , Satoshi Iwahashi , Takeshi Suzuki , Keiichi Higeta , Kazuo Kanetani
发明人： Shigeru Nakahara , Satoshi Iwahashi , Takeshi Suzuki , Keiichi Higeta , Kazuo Kanetani
IPC分类号： G11C700
CPC分类号： G11C7/109 , G11C7/1045 , G11C7/1078 , G11C7/1087 , G11C2207/104
摘要： The invention provides a semiconductor integrated circuit device on which a RAM macro capable of selecting an operation mode adapted to improved ease of use, response, or low power consumption or selecting an input setup value is mounted. In a first operation mode of a RAM macro, a timing of receiving an input signal is set as a first timing. In a second operation mode, a timing of receiving an input signal is set to a second timing later than the first timing. In a semiconductor integrated circuit device including an input circuit for receiving an input signal and a decoder circuit for decoding an output signal of the input circuit, the input circuit is activated on the basis of a first signal and the decoder circuit is activated on the basis of a second signal.
摘要翻译：本发明提供了一种半导体集成电路装置，其上安装有能够选择适于提高易用性，易于使用或低功耗或选择输入设定值的操作模式的RAM宏。在RAM宏的第一操作模式中，接收输入信号的定时被设置为第一定时。在第二操作模式中，将接收输入信号的定时设置为晚于第一定时的第二定时。在包括用于接收输入信号的输入电路和用于对输入电路的输出信号进行解码的解码器电路的半导体集成电路装置中，基于第一信号激活输入电路，并且解码器电路基于的第二信号。

10. 发明授权

US06826107B2 High voltage insertion in flash memory cards 有权
公开(公告)号：US06826107B2
公开(公告)日：2004-11-30
申请号：US10209644
申请日：2002-08-01
申请人： Ran Dvir , Zeev Cohen
发明人： Ran Dvir , Zeev Cohen
IPC分类号： G11C700
CPC分类号： G11C16/30 , G11C5/147
摘要： A flash memory card including a controller, at least one control pad, at least one memory, and a high voltage switch logic module in communication with the at least one control pad, the controller and the at least one memory, the high voltage switch logic module being adapted to selectively route voltage from the at least one control pad to one of the controller and the at least one memory. If the voltage input to the at least one control pad does not exceed a predefined level, then the voltage may be routed from the at least one control pad to the controller. If the voltage input to the at least one control pad exceeds the predefined level, then the voltage may be routed from the at least one control pad to the at least one memory.

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