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41. 发明授权

US07547959B2 Bipolar junction transistor and manufacturing method thereof 失效
标题翻译：双极结晶体管及其制造方法
公开(公告)号：US07547959B2
公开(公告)日：2009-06-16
申请号：US11646828
申请日：2006-12-27
申请人： Nam Joo Kim
发明人： Nam Joo Kim
IPC分类号： H01L27/082 , H01L27/102 , H01L29/70
CPC分类号： H01L29/0692 , H01L29/0821 , H01L29/1004 , H01L29/66272 , H01L29/732
摘要： An improved bipolar junction transistor and a method for manufacturing the same are provided. The bipolar junction transistor includes: a buried layer and a high concentration N-type collector region in a P-type semiconductor substrate; a low concentration P-type base region in the semiconductor substrate above the buried layer; a first high concentration P-type base region along an edge of the low concentration P-type base region; a second high concentration P-type base region at a center of the low concentration P-type base region; a high concentration N-type emitter region between the first and second high concentration base regions; and insulating layer spacers between the high concentration base regions and the high concentration emitter regions. In the bipolar junction transistor, the emitter-base distance can be reduced using a trench and an insulating layer spacer. This may improve base voltage and high-speed response characteristics.
摘要翻译：提供一种改进的双极结型晶体管及其制造方法。双极结型晶体管包括：P型半导体衬底中的掩埋层和高浓度N型集电极区域; 在掩埋层上方的半导体衬底中的低浓度P型基极区域; 沿着低浓度P型基区的边缘的第一高浓度P型基区; 位于低浓度P型基区的中心的第二高浓度P型碱基区域; 第一和第二高浓度基区之间的高浓度N型发射极区; 以及高浓度基极区域和高浓度发射极区域之间的绝缘层间隔物。在双极结型晶体管中，可以使用沟槽和绝缘层间隔物来减小发射极 - 基极距离。这可以提高基极电压和高速响应特性。

42. 发明授权

US07541641B2 Gate structure in a trench region of a semiconductor device and method for manufacturing the same 有权
标题翻译：半导体器件的沟槽区域中的栅极结构及其制造方法
公开(公告)号：US07541641B2
公开(公告)日：2009-06-02
申请号：US11646837
申请日：2006-12-27
申请人： Kwang Young Ko
发明人： Kwang Young Ko
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119
CPC分类号： H01L29/66621 , H01L21/28114 , H01L29/42376 , H01L29/66553 , H01L29/7834
摘要： Disclosed are a gate structure in a trench region of a semiconductor device and method for manufacturing the same. The semiconductor device includes a pair of drift regions formed in a semiconductor substrate; a trench region formed between the pair of drift regions; an oxide layer spacer on sidewalls of the trench region; a gate formed in the trench region; and a source and a drain formed in the pair of the drift regions, respectively.
摘要翻译：公开了半导体器件的沟槽区域中的栅极结构及其制造方法。半导体器件包括形成在半导体衬底中的一对漂移区域; 形成在所述一对漂移区域之间的沟槽区域; 在沟槽区域的侧壁上的氧化物层间隔物; 形成在沟槽区域中的栅极; 以及分别形成在该对漂移区域中的源极和漏极。

43. 发明授权

US07528455B2 Narrow width metal oxide semiconductor transistor 有权
标题翻译：窄宽度的金属氧化物半导体晶体管
公开(公告)号：US07528455B2
公开(公告)日：2009-05-05
申请号：US11646727
申请日：2006-12-27
申请人： Jung Ho Ahn
发明人： Jung Ho Ahn
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L31/113 , H01L31/119 , H01L27/10 , H01L29/739 , H01L29/73
CPC分类号： H01L29/41758 , H01L29/78
摘要： Disclosed is a semiconductor transistor for enhancing performance of PMOS and NMOS transistors, particularly current driving performance, while reducing a narrow width effect. A narrow width MOS transistor includes: a channel of which width is W0 and length is L0; an active area including source and drain areas formed at both sides with the channel as a center; a gate insulating layer formed on the channel; a gate conductor formed on the gate insulating layer and intersecting the active area; a first additional active area of width is larger than that W0 of the channel as an active area added to the source area; and a second additional active area of width is larger than that W0 of the channel as an active area added to the drain area. When the structure of the transistor having the additional active areas is applied to NMOS and PMOS transistors, a driving current is represented as 107.27% and 103.31%, respectively. Accordingly, the driving currents of both PMOS and NMOS transistors are enhanced.
摘要翻译：公开了一种用于增强PMOS和NMOS晶体管的性能的半导体晶体管，特别是电流驱动性能，同时减小窄宽度效应。窄宽度的MOS晶体管包括：宽度为W0且长度为L0的沟道; 一个有效区域，包括以通道为中心形成在两侧的源区和漏区; 形成在所述通道上的栅极绝缘层; 栅极导体，形成在栅极绝缘层上并与有源区相交; 宽度的第一附加有效区域大于作为添加到源区域的活动区域的信道的W0; 并且宽度的第二附加有源区域大于作为添加到漏极区域的有源区域的沟道的W0。当具有附加有源区的晶体管的结构被施加到NMOS和PMOS晶体管时，驱动电流分别表示为107.27％和103.31％。因此，增加了PMOS和NMOS晶体管的驱动电流。

44. 发明授权

US07514337B2 Semiconductor device using EPI-layer and method of forming the same 有权
标题翻译：使用EPI层的半导体器件及其形成方法
公开(公告)号：US07514337B2
公开(公告)日：2009-04-07
申请号：US11503020
申请日：2006-08-11
申请人： Dae Ho Jeong
发明人： Dae Ho Jeong
IPC分类号： H01L21/76
CPC分类号： H01L21/823807 , H01L21/823878 , H01L29/78
摘要： A method of fabricating a semiconductor device includes forming a pad oxide film and a nitride film on a semiconductor substrate; exposing the semiconductor substrate by selectively etching the pad oxide film and the nitride film; forming a trench in the exposed semiconductor substrate; forming a gap-fill dielectric film in the trench; exposing an active area of the semiconductor substrate by removing the pad oxide film and the nitride film; forming an epitaxial layer including a dopant in the exposed active area; forming a gate electrode on the epitaxial layer; and forming source and drain regions in the active area beside the gate electrode. The semiconductor device can prevent surface damage of a semiconductor substrate, may occur when performing ion implantation for threshold voltage control, and does not require annealing after ion implantation. Additionally, the semiconductor device can enhance an isolation effect by protecting an oxide film in a corner portion of the STI, to prevent an occurrence of a moat phenomenon in the STI, and to prevent the damage of the gap-fill dielectric film.
摘要翻译：制造半导体器件的方法包括在半导体衬底上形成衬垫氧化膜和氮化物膜; 通过选择性地蚀刻衬垫氧化物膜和氮化物膜来暴露半导体衬底; 在所述暴露的半导体衬底中形成沟槽; 在沟槽中形成间隙填充电介质膜; 通过去除衬垫氧化膜和氮化物膜来暴露半导体衬底的有源区; 在所述暴露的有源区中形成包括掺杂剂的外延层; 在外延层上形成栅电极; 以及在栅电极旁边的有源区中形成源区和漏区。半导体器件可以防止半导体衬底的表面损伤，当进行用于阈值电压控制的离子注入时可能发生，并且在离子注入后不需要退火。此外，半导体器件可以通过保护STI的拐角部分中的氧化膜来增强隔离效果，以防止STI中出现沟槽现象，并且防止间隙填充电介质膜的损坏。

45. 发明授权

US07507647B2 Method of manufacturing a high voltage semiconductor device including a deep well and a gate oxide layer simultaneously 失效
标题翻译：同时制造包括深阱和栅极氧化物层的高电压半导体器件的方法
公开(公告)号：US07507647B2
公开(公告)日：2009-03-24
申请号：US11313693
申请日：2005-12-22
申请人： Tae-Hong Lim
发明人： Tae-Hong Lim
IPC分类号： H01L21/425
CPC分类号： H01L21/823878 , H01L21/823892
摘要： A method of manufacturing a high voltage semiconductor device including forming a P-type region implanted with P-type impurities and an N-type region implanted with N-type impurities in a silicon substrate. The method further includes forming a silicon nitride layer pattern and a pad oxide layer pattern to expose a surface of the silicon substrate, forming a trench by etching the exposed silicon substrate using the silicon nitride layer pattern as an etch mask, forming a trench oxide layer pattern in the trench by removing the silicon nitride layer pattern and the pad oxide layer pattern, and simultaneously forming a deep P-well and a deep N-well by driving P-type impurities in the P-type region and N-type impurities in the N-type region into the silicon substrate, while forming a gate oxide layer on a silicon substrate including the trench oxide layer pattern.
摘要翻译：一种制造高电压半导体器件的方法，包括在硅衬底中形成注入了P型杂质的P型区域和注入N型杂质的N型区域。该方法还包括形成氮化硅层图案和焊盘氧化物层图案以暴露硅衬底的表面，通过使用氮化硅层图案蚀刻暴露的硅衬底作为蚀刻掩模形成沟槽，形成沟槽氧化物层通过去除氮化硅层图案和焊盘氧化物层图案在沟槽中形成图案，并且通过驱动P型区域中的P型杂质和N型杂质同时形成深P阱和深N阱同时在包括沟槽氧化物层图案的硅衬底上形成栅极氧化层，形成硅衬底的N型区域。

46. 发明授权

US07507625B2 Flash memory device and method for manufacturing the same 有权
标题翻译：闪存装置及其制造方法
公开(公告)号：US07507625B2
公开(公告)日：2009-03-24
申请号：US11474202
申请日：2006-06-23
申请人： Yeong-Sil Kim
发明人： Yeong-Sil Kim
IPC分类号： H01L21/8247
CPC分类号： H01L29/7881 , H01L29/0657 , H01L29/66825
摘要： A flash memory device, and a manufacturing method thereof, having advantages of protecting sidewalls of a floating gate and a control gate and preventing a recess of an active area of a source region are provided. The method includes forming a tunneling oxide layer on an active region of a semiconductor substrate, forming a floating gate, a gate insulation layer, and a control gate on the tunneling oxide layer, forming insulation sidewall spacers on sides of the floating gate and the control gate, and removing at least portions of the tunneling oxide layer and the device isolation layer so as to expose the active region.
摘要翻译：提供一种闪存器件及其制造方法，具有保护浮置栅极和控制栅极的侧壁并防止源极区域的有源区域的凹陷的优点。该方法包括在半导体衬底的有源区上形成隧道氧化物层，在隧道氧化物层上形成浮置栅极，栅极绝缘层和控制栅极，在浮动栅极的侧面形成绝缘侧壁间隔物，并且去除隧穿氧化物层和器件隔离层的至少一部分以暴露有源区。

47. 发明授权

US07501319B2 Manufacturing a semiconductor device including sidewall floating gates 失效
标题翻译：制造包括侧壁浮动栅极的半导体器件
公开(公告)号：US07501319B2
公开(公告)日：2009-03-10
申请号：US11731124
申请日：2007-03-30
申请人： Jin Hyo Jung
发明人： Jin Hyo Jung
IPC分类号： H01L21/8238
CPC分类号： H01L27/11521 , H01L21/26586 , H01L21/823814 , H01L21/823828 , H01L21/823864 , H01L27/115 , H01L29/66484 , H01L29/66553 , H01L29/66583 , H01L29/66643 , H01L29/7831 , H01L29/7833
摘要： A semiconductor device and a fabricating method thereof are disclosed. The semiconductor device includes polysilicon gate electrodes, a gate oxide layer, sidewall floating gates, a block oxide layer, source/drain areas, and sidewall spacers. In addition, the method includes the steps of: forming a block dielectric layer and a sacrificial layer on a semiconductor substrate; forming trenches by etching the sacrificial layer; forming sidewall floating gates on lateral faces of the trenches; forming a block oxide layer on the sidewall floating gates; forming polysilicon gate electrodes by a patterning process; removing the sacrificial layer; forming source/drain areas by implanting impurity ions into the resulting structure; injecting carriers or electric charges into the sidewall floating gates; and forming spacers on lateral faces of the polysilicon gate electrodes and the sidewall floating gates.
摘要翻译：公开了一种半导体器件及其制造方法。半导体器件包括多晶硅栅电极，栅极氧化层，侧壁浮置栅极，块状氧化物层，源极/漏极区域和侧壁间隔物。此外，该方法包括以下步骤：在半导体衬底上形成块介质层和牺牲层; 通过蚀刻牺牲层形成沟槽; 在沟槽的侧面上形成侧壁浮动栅; 在所述侧壁浮动栅上形成块状氧化物层; 通过图案化工艺形成多晶硅栅电极; 去除牺牲层; 通过将杂质离子注入到所得结构中来形成源极/漏极区域; 将载体或电荷注入到侧壁浮动门中; 以及在多晶硅栅极电极和侧壁浮动栅极的侧面上形成间隔物。

48. 发明授权

US07491571B2 Method of manufacturing an image sensor having microlenses formed under high pressure 失效
标题翻译：制造具有在高压下形成的微透镜的图像传感器的方法
公开(公告)号：US07491571B2
公开(公告)日：2009-02-17
申请号：US11611273
申请日：2006-12-15
申请人： Sang Sik Kim
发明人： Sang Sik Kim
IPC分类号： H01L21/00
CPC分类号： H01L27/14632 , H01L27/14627 , H01L27/14685 , H01L27/14687
摘要： A method for manufacturing an image sensor is provided. The method includes: forming a plurality of photodiodes on a semiconductor substrate; forming an interlayer dielectric on the semiconductor substrate; forming a color filter layer on the interlayer dielectric; forming a planarization layer on the color filter layer; and forming microlenses on the planarization layer under high temperature and pressure.
摘要翻译：提供了一种用于制造图像传感器的方法。该方法包括：在半导体衬底上形成多个光电二极管; 在半导体衬底上形成层间电介质; 在所述层间电介质上形成滤色器层; 在所述滤色器层上形成平坦化层; 并在高温高压下在平坦化层上形成微透镜。

49. 发明授权

US07488672B2 Well photoresist pattern of semiconductor device and method for forming the same 失效
标题翻译：半导体器件的良好的光致抗蚀剂图案及其形成方法
公开(公告)号：US07488672B2
公开(公告)日：2009-02-10
申请号：US11493379
申请日：2006-07-25
申请人： Sung Moo Kim
发明人： Sung Moo Kim
IPC分类号： H01L21/425
CPC分类号： H01L21/0274 , H01L21/0273 , H01L21/266
摘要： Disclosed is a well photoresist pattern of a semiconductor, and the fabrication method thereof. The method includes the steps of: (a) forming a sacrificial oxide layer on a semiconductor substrate; (b) applying a primer on the sacrificial oxide layer; (c) applying a photoresist on the primer; (d) soft-baking the photoresist; (e) exposing the photoresist to light by defocusing the DOF (depth of focus) of the light transmitted to the substrate; (f) post exposure baking the photoresist; (g) developing the photo-exposed photoresist to form a well photoresist pattern; and (h) hard-baking the well photoresist pattern. It is preferable that the exposure is performed by plus(+) defocusing of light.
摘要翻译：公开了半导体的良好的光致抗蚀剂图案及其制造方法。该方法包括以下步骤：（a）在半导体衬底上形成牺牲氧化物层; （b）在所述牺牲氧化物层上施加底漆; （c）在底漆上施加光致抗蚀剂; （d）软化光刻胶; （e）通过使透射到衬底的光的DOF（焦深）散焦而使光致抗蚀剂曝光; （f）曝光后烘烤光刻胶; （g）显影曝光的光致抗蚀剂以形成良好的光致抗蚀剂图案; 和（h）硬烘烤光致抗蚀剂图案。优选的是，通过加（+）光的散焦进行曝光。

50. 发明授权

US07485555B2 Methods for forming a P-type polysilicon layer in a semiconductor device 有权
标题翻译：在半导体器件中形成P型多晶硅层的方法
公开(公告)号：US07485555B2
公开(公告)日：2009-02-03
申请号：US11291948
申请日：2005-12-01
申请人： Jae-Suk Lee
发明人： Jae-Suk Lee
IPC分类号： H01L21/22 , H01L21/38
CPC分类号： H01L21/02579 , H01L21/02532
摘要： A P-type polysilicon layer having a stable and desired resistivity is formed by alternately depositing a plurality of silicon atom layers and a plurality of group IIIA element atom layers on a semiconductor substrate by atomic layer deposition, and thereafter forming a P-type polysilicon layer by thermally diffusing the plurality of group IIIA element atom layers into the plurality of silicon atom layers. The plurality of group IIIA element atom layers may comprise Al, Ga, In, and/or Tl.
摘要翻译：通过原子层沉积在半导体衬底上交替沉积多个硅原子层和多个IIIA族元素原子层来形成具有稳定和期望电阻率的P型多晶硅层，然后形成P型多晶硅层通过将多个IIIA族元素原子层热扩散到多个硅原子层中。多个IIIA族元素原子层可以包括Al，Ga，In和/或Tl。

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