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41. 发明申请

US20050064681A1 Support structure for thinning semiconductor substrates and thinning methods employing the support structure 有权
标题翻译：用于减薄半导体衬底的支撑结构和采用支撑结构的薄化方法
公开(公告)号：US20050064681A1
公开(公告)日：2005-03-24
申请号：US10666742
申请日：2003-09-19
申请人： Alan Wood , Warren Farnworth , David Hembree , Sidney Rigg , William Hiatt , Peter Benson , Kyle Kirby , Salman Akram
发明人： Alan Wood , Warren Farnworth , David Hembree , Sidney Rigg , William Hiatt , Peter Benson , Kyle Kirby , Salman Akram
IPC分类号： E21B43/02 , G03F7/00 , G03F7/004 , H01L21/30 , H01L21/46
CPC分类号： G03F7/0037 , B33Y30/00 , B33Y70/00 , B33Y80/00 , G03F7/0047
摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion which extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member which substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface. Assemblies that include the support structure and a semiconductor substrate are also within the scope of the present invention, as are methods for forming the support structures and thinning and post-thinning processes that include use of the support structures.
摘要翻译：在半导体衬底的薄化或后研磨以及后稀化处理期间与半导体衬底一起使用的支撑结构包括基本上沿半导体衬底的外周延伸并且围绕半导体衬底的外周延伸的部分，以使薄化半导体基板具有刚性。支撑结构可以被配置为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。包括支撑结构和半导体衬底的组件也在本发明的范围内，形成支撑结构的方法和包括使用支撑结构的减薄和后变薄工艺也是如此。

42. 发明申请

US20050018336A1 Double-attribute method of encoding and decoding magnetic data 失效
公开(公告)号：US20050018336A1
公开(公告)日：2005-01-27
申请号：US10919821
申请日：2004-08-17
申请人： Kyle Kirby
发明人： Kyle Kirby
IPC分类号： G11B20/08 , G11B20/14
CPC分类号： G11B20/1407 , G11B20/08 , G11B20/14
摘要： A method of encoding and decoding data involving the simultaneous application of pulse width modulation and pulse position modulation systems to data intended for storage on a magnetic disk medium.

43. 发明申请

US20050012221A1 Semiconductor interconnect having conductive spring contacts, method of fabrication, and test systems incorporating the interconnect 有权
标题翻译：具有导电弹簧触点的半导体互连，制造方法和结合了互连的测试系统
公开(公告)号：US20050012221A1
公开(公告)日：2005-01-20
申请号：US10619650
申请日：2003-07-14
申请人： Kyle Kirby , Warren Farnworth
发明人： Kyle Kirby , Warren Farnworth
IPC分类号： G01R1/067 , H01L23/48 , H01L23/498 , H05K3/32 , H05K3/40
CPC分类号： G01R1/06733 , B33Y70/00 , B33Y80/00 , G01R1/06711 , G01R1/07314 , G01R3/00 , H01L23/49811 , H01L24/72 , H01L2224/05571 , H01L2224/05573 , H01L2224/13011 , H01L2224/13019 , H01L2924/00014 , H01L2924/01004 , H01L2924/01005 , H01L2924/01006 , H01L2924/01009 , H01L2924/01012 , H01L2924/01013 , H01L2924/01029 , H01L2924/01032 , H01L2924/01033 , H01L2924/01042 , H01L2924/01047 , H01L2924/01072 , H01L2924/01073 , H01L2924/01074 , H01L2924/01082 , H01L2924/12042 , H01L2924/14 , H05K3/326 , H05K3/4092 , H01L2924/00 , H01L2224/05599
摘要： An interconnect for testing a semiconductor component includes a substrate, and interconnect contacts on the substrate configured to electrically engage component contacts on a semiconductor component. Each interconnect contact includes a compliant conductive layer formed as a conductive spring element. In addition, the complaint conductive layer includes a tip for engaging the component contact and a spring segment portion for resiliently supporting the tip. A method for fabricating the interconnect includes the steps of shaping the substrate, forming a conductive layer on a shaped portion of the substrate and removing at least some of the shaped portion. The shaped portion can comprise a raised step or dome, or a shaped recess in the substrate. The conductive layer can comprise a metal, a conductive polymer or a polymer tape can include a penetrating structure or penetrating particles. The interconnect can be used to construct wafer level test systems, and die level test systems as well, for semiconductor components such as wafers, dice and packages.
摘要翻译：用于测试半导体部件的互连件包括衬底，以及被配置为电接合半导体部件上的部件触点的衬底上的互连触点。每个互连触点包括形成为导电弹簧元件的柔性导电层。此外，投诉导电层包括用于接合部件触点的尖端和用于弹性地支撑尖端的弹簧部分部分。一种用于制造互连的方法包括以下步骤：对衬底进行成形，在衬底的成形部分上形成导电层，并移除至少部分成形部分。成形部分可以包括升高的台阶或圆顶，或者基板中的成形凹部。导电层可以包括金属，导电聚合物或聚合物带可以包括穿透结构或穿透颗粒。互连可以用于构建晶片级测试系统和芯片级测试系统，用于诸如晶片，芯片和封装的半导体元件。

44. 发明授权

US07968460B2 Semiconductor with through-substrate interconnect 有权
标题翻译：半导体与通孔基板互连
公开(公告)号：US07968460B2
公开(公告)日：2011-06-28
申请号：US12142251
申请日：2008-06-19
申请人： Kyle Kirby , Kunal Parekh
发明人： Kyle Kirby , Kunal Parekh
IPC分类号： H01L21/44
CPC分类号： H01L21/743 , H01L21/26513 , H01L21/76802 , H01L21/76831 , H01L21/76877 , H01L21/76895 , H01L21/76898 , H01L21/823475 , H01L23/481 , H01L23/49816 , H01L27/0694 , H01L27/10888 , H01L27/10894 , H01L29/66568 , H01L29/78 , H01L2224/02372 , H01L2224/0401 , H01L2224/05548
摘要： Semiconductor devices are described that have a metal interconnect extending vertically through a portion of the device to the back side of a semiconductor substrate. A top region of the metal interconnect is located vertically below a horizontal plane containing a metal routing layer. Method of fabricating the semiconductor device can include etching a via into a semiconductor substrate, filling the via with a metal material, forming a metal routing layer subsequent to filling the via, and removing a portion of a bottom of the semiconductor substrate to expose a bottom region of the metal filled via.
摘要翻译：描述了具有垂直延伸穿过器件的一部分到半导体衬底背面的金属互连的半导体器件。金属互连的顶部区域垂直位于包含金属布线层的水平平面的下方。制造半导体器件的方法可以包括将通孔蚀刻到半导体衬底中，用金属材料填充通孔，在填充通孔之后形成金属布线层，以及去除半导体衬底的底部的一部分以露出底部金属填充通孔的区域。

45. 发明申请

US20090215263A1 METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH 有权
标题翻译：在深层硅干蚀刻中增加蚀刻速率的方法
公开(公告)号：US20090215263A1
公开(公告)日：2009-08-27
申请号：US12434882
申请日：2009-05-04
申请人： Kyle Kirby , Swarnal Borthakur
发明人： Kyle Kirby , Swarnal Borthakur
IPC分类号： H01L21/3205 , H01L21/308
CPC分类号： H01L21/76898 , H01L21/3083
摘要： A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.
摘要翻译：提出了通过改变蚀刻掩模的几何形状在深硅干蚀刻期间提高蚀刻速率的方法。通过稍微改变蚀刻掩模的形状，在使用椭圆形蚀刻掩模的一个区域中，与使用不同几何形状的蚀刻掩模的其它区域相比，即使露出几乎相同量的硅，蚀刻速率增加。此外，可以通过使用不同的几何形状的蚀刻掩模来控制通孔的深度，同时保持所有通孔的直径几乎相同的尺寸。

46. 发明申请

US20090159208A1 METHOD OF FORMING TEMPORARY CARRIER STRUCTURE AND ASSOCIATED RELEASE TECHNIQUES 有权
标题翻译：形成临时载体结构和相关释放技术的方法
公开(公告)号：US20090159208A1
公开(公告)日：2009-06-25
申请号：US11963230
申请日：2007-12-21
申请人： Kyle Kirby
发明人： Kyle Kirby
IPC分类号： B32B38/10
CPC分类号： H01L21/6835 , H01L2221/68318 , Y10T156/1064 , Y10T156/1082 , Y10T156/1111
摘要： A method of forming a temporary carrier structure is disclosed which includes forming a plurality of recesses in a carrier structure, the recesses extending to a depth that is less than a thickness of the carrier structure, forming a dissolvable material in the recesses and above a first surface of the carrier structure, securing a thin substrate above the first surface of the carrier structure using the dissolvable material to secure the thin substrate in place, performing at least one process operation on a second surface of the carrier structure to expose the dissolvable material in the recesses and contacting the exposed dissolvable material with a release agent so as to dissolve at least a portion of the dissolvable material.
摘要翻译：公开了一种形成临时载体结构的方法，其包括在载体结构中形成多个凹部，所述凹部延伸到小于载体结构的厚度的深度，在凹部中形成可溶解材料，并且在第一载体结构的表面，使用可溶解材料将薄衬底固定在载体结构的第一表面上，以将薄衬底固定就位，在载体结构的第二表面上进行至少一个工艺操作以将可溶解材料暴露在所述凹部和暴露的可溶解材料与脱模剂接触以溶解至少一部分可溶解材料。

47. 发明申请

US20090032964A1 System and method for providing semiconductor device features using a protective layer 审中-公开
标题翻译：使用保护层提供半导体器件特征的系统和方法
公开(公告)号：US20090032964A1
公开(公告)日：2009-02-05
申请号：US11888122
申请日：2007-07-31
申请人： Warren Farnworth , Kyle Kirby
发明人： Warren Farnworth , Kyle Kirby
IPC分类号： H01L23/48 , H01L21/4763
CPC分类号： H01L21/76898 , H01L23/481 , H01L23/5226 , H01L23/525 , H01L24/10 , H01L24/12 , H01L24/13 , H01L2224/0401 , H01L2224/0557 , H01L2224/13 , H01L2224/13025 , H01L2224/13099 , H01L2224/16 , H01L2924/0002 , H01L2924/01033 , H01L2924/14 , H01L2924/19042 , H01L2924/3025 , H01L2224/05552 , H01L2924/00
摘要： Present embodiments relate to systems and methods for providing semiconductor device features using a protective layer during coating operations. One embodiment includes a method comprising providing a substrate with a hole formed partially therethrough, the hole comprising an opening in a first side of the substrate. Additionally, the method comprises disposing a protective layer over the first side of the substrate, removing a portion of the protective layer over at least a portion of the opening to provide access to the hole, and filling at least a portion of the hole with a fill material.
摘要翻译：本实施例涉及在涂覆操作期间使用保护层提供半导体器件特征的系统和方法。一个实施例包括一种方法，其包括提供基底部分穿过其中形成的孔，所述孔包括在所述基底的第一侧中的开口。另外，该方法包括在衬底的第一侧上设置保护层，在开口的至少一部分上移除保护层的一部分以提供对孔的接近，以及用孔填充孔的至少一部分填充材料。

48. 发明申请

US20080299770A1 METHOD FOR INCREASING ETCH RATE DURING DEEP SILICON DRY ETCH 失效
标题翻译：在深层硅干蚀刻中增加蚀刻速率的方法
公开(公告)号：US20080299770A1
公开(公告)日：2008-12-04
申请号：US11756120
申请日：2007-05-31
申请人： Kyle Kirby , Swarnal Borthakur
发明人： Kyle Kirby , Swarnal Borthakur
IPC分类号： H01L21/44
CPC分类号： H01L21/76898 , H01L21/3083
摘要： A method of increasing etch rate during deep silicon dry etch by altering the geometric shape of the etch mask is presented. By slightly altering the shape of the etch mask, the etch rate is increased in one area where an oval etch mask is used as compared to another areas where different geometrically-shaped etch masks are used even though nearly the same amount of silicon is exposed. Additionally, the depth of the via can be controlled by using different geometrically-shaped etch masks while maintaining virtually the same size in diameter for all the vias.
摘要翻译：提出了通过改变蚀刻掩模的几何形状在深硅干蚀刻期间提高蚀刻速率的方法。通过稍微改变蚀刻掩模的形状，在使用椭圆形蚀刻掩模的一个区域中，与使用不同几何形状的蚀刻掩模的其它区域相比，即使露出几乎相同量的硅，蚀刻速率增加。此外，可以通过使用不同的几何形状的蚀刻掩模来控制通孔的深度，同时保持所有通孔的直径几乎相同的尺寸。

49. 发明申请

US20080029851A1 METHODS OF FORMING CONDUCTIVE VIAS AND METHODS OF FORMING MULTICHIP MODULES INCLUDING SUCH CONDUCTIVE VIAS 有权
标题翻译：形成导电VIAS的方法和形成包括这种导电VIAS的多模块模块的方法
公开(公告)号：US20080029851A1
公开(公告)日：2008-02-07
申请号：US11868899
申请日：2007-10-08
申请人： Kyle Kirby , Warren Farnworth
发明人： Kyle Kirby , Warren Farnworth
IPC分类号： H01L29/40
CPC分类号： B82Y10/00 , H01L21/76898 , H01L23/481 , H01L25/0657 , H01L25/50 , H01L2221/1094 , H01L2224/05001 , H01L2224/05009 , H01L2224/05548 , H01L2224/0557 , H01L2224/16 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2225/06551 , H01L2924/00014 , H01L2924/01019 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/09701 , H01L2224/05599 , H01L2224/05099
摘要： A method of forming a multiconductor via includes forming at least one seed layer in at least one through-hole of a substrate, selectively patterning the seed layer to form a plurality of laterally separated regions, and depositing metal upon the regions. Alternatively, a through-hole may be substantially filled with dielectric material, a plurality of smaller through-holes may be formed in the dielectric material, and conductive material may be deposited in the smaller holes. Another method includes forming laterally separated protruding structures in a cavity of a substrate, depositing conductive material over the structures and dielectric material between the structures, and thinning the substrate. Alternatively, conductive nanotubes may be formed in the cavity, and dielectric material may be deposited that surrounds the nanotubes. A method of forming a multichip module includes forming at least one via extending through a plurality of stacked dice that includes a plurality of conductive elements.
摘要翻译：形成多导体通孔的方法包括在衬底的至少一个通孔中形成至少一个种子层，选择性地图案化种子层以形成多个横向分离的区域，并在该区域上沉积金属。或者，通孔可以基本上填充有介电材料，可以在电介质材料中形成多个较小的通孔，并且导电材料可以沉积在较小的孔中。另一种方法包括在衬底的空腔中形成横向分离的突出结构，在结构之间沉积导电材料并在该结构之间沉积电介质材料，并使衬底变薄。或者，可以在空腔中形成导电纳米管，并且可以沉积围绕纳米管的电介质材料。一种形成多芯片模块的方法包括形成至少一个通过包括多个导电元件的多个堆叠的骰子延伸的通孔。

50. 发明申请

US20080011815A1 METHODS FOR PLACING SUBSTRATES IN CONTACT WITH MOLTEN SOLDER 审中-公开
标题翻译：用于安装与MOLTEN SOLDER接触的基板的方法
公开(公告)号：US20080011815A1
公开(公告)日：2008-01-17
申请号：US11777137
申请日：2007-07-12
申请人： Kyle Kirby , Salman Akram , Daniel Cram , Roy Lange , Warren Farnworth
发明人： Kyle Kirby , Salman Akram , Daniel Cram , Roy Lange , Warren Farnworth
IPC分类号： B23K31/02
CPC分类号： B23K1/085 , B23K1/0016 , B23K3/0653 , B23K2101/40
摘要： Methods and devices for placing a semiconductor wafer or other substrate in contact with solder are described. A wave soldering apparatus includes a solder bath, a nozzle for producing a solder wave, and a jig for orienting a substrate in a substantially vertical orientation and placing the substrate in contact with a cascading solder wave. In another wave soldering apparatus, a jig orients a semiconductor wafer in a substantially horizontal orientation in contact with the solder wave. Another soldering apparatus includes a tank comprising molten solder and a fixture configured to orient one or more semiconductor wafers in a substantially vertical orientation. Methods of placing semiconductor wafers or other substrates in contact with solder using the devices of the present invention are also disclosed.
摘要翻译：描述了将半导体晶片或其它基板与焊料接触的方法和装置。波峰焊装置包括焊料槽，用于产生焊波的喷嘴和用于使基板垂直定向的夹具，并使基板与级联焊波接触。在另一种波峰焊装置中，夹具使得与焊波接触的大致水平取向的半导体晶片。另一个焊接装置包括一个包含熔融焊料和一个被配置为使一个或多个半导体晶片呈基本垂直取向取向的夹具的罐。还公开了使用本发明的装置将半导体晶片或其它基板与焊料接触的方法。

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