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1. 发明授权

US08816405B2 Elevated pocket pixels, imaging devices and systems including the same and method of forming the same 有权
标题翻译：袋状像素升高，成像装置和系统的构成及其形成方法
公开(公告)号：US08816405B2
公开(公告)日：2014-08-26
申请号：US13084649
申请日：2011-04-12
申请人： Salman Akram
发明人： Salman Akram
IPC分类号： H01L27/148
CPC分类号： H01L27/14607 , H01L27/146 , H01L27/14601 , H01L27/14603 , H01L27/14605 , H01L27/14621 , H01L27/14627 , H01L27/14632 , H01L27/14643 , H01L27/14645 , H01L27/14647 , H01L27/14685 , H01L27/14687 , H01L27/14689 , H01L27/14692 , H01L31/02162 , H01L31/022408 , H01L31/028 , H01L31/0288 , H01L31/0352 , H01L31/035281 , H01L31/03762 , H01L31/1804
摘要： An elevated photosensor for image sensors and methods of forming the photosensor. The photosensor may have light sensors having indentation features including, but not limited to, v-shaped, u-shaped, or other shaped features. Light sensors having such an indentation feature can redirect incident light that is not absorbed by one portion of the photosensor to another portion of the photosensor for additional absorption. In addition, the elevated photosensors reduce the size of the pixel cells while reducing leakage, image lag, and barrier problems.
摘要翻译：用于图像传感器的升高的光电传感器和形成光电传感器的方法。光传感器可以具有具有凹陷特征的光传感器，包括但不限于v形，u形或其它成形特征。具有这种压痕特征的光传感器可以将不被光电传感器的一部分吸收的入射光重定向到光传感器的另一部分以便额外吸收。此外，升高的光电传感器减小像素单元的尺寸，同时减少泄漏，图像滞后和屏障问题。

2. 发明申请

US20120135567A1 METHODS AND APPARATUSES FOR TRANSFERRING HEAT FROM STACKED MICROFEATURE DEVICES 有权
标题翻译：用于从堆叠微型设备传输热量的方法和装置
公开(公告)号：US20120135567A1
公开(公告)日：2012-05-31
申请号：US13367158
申请日：2012-02-06
申请人： Salman Akram , David R. Hembree
发明人： Salman Akram , David R. Hembree
IPC分类号： H01L21/98 , F28F7/00
CPC分类号： H01L25/0657 , H01L2224/05001 , H01L2224/05009 , H01L2224/05568 , H01L2224/16 , H01L2225/06513 , H01L2225/06541 , H01L2225/06589 , H01L2924/00014 , H01L2224/05599 , H01L2224/05099
摘要： Methods and apparatuses for transferring heat from stacked microfeature devices are disclosed herein. In one embodiment, a microfeature device assembly comprises a support member having terminals and a first microelectronic die having first external contacts carried by the support member. The first external contacts are operatively coupled to the terminals on the support member. The assembly also includes a second microelectronic die having integrated circuitry and second external contacts electrically coupled to the first external contacts. The first die is between the support member and the second die. The assembly can further include a heat transfer unit between the first die and the second die. The heat transfer unit includes a first heat transfer portion, a second heat transfer portion, and a gap between the first and second heat transfer portions such that the first external contacts and the second external contacts are aligned with the gap.
摘要翻译：本文公开了用于从堆叠的微特征装置传递热量的方法和装置。在一个实施例中，微特征装置组件包括具有端子的支撑构件和具有由支撑构件承载的第一外部触点的第一微电子模具。第一外部触点可操作地耦合到支撑构件上的端子。组件还包括具有集成电路的第二微电子管芯和电耦合到第一外部触点的第二外部触头。第一模具在支撑构件和第二模具之间。组件还可以包括在第一模具和第二模具之间的传热单元。传热单元包括第一传热部分，第二传热部分和第一和第二传热部分之间的间隙，使得第一外部接触部和第二外部接触部与间隙对准。

3. 发明授权

US07960829B2 Support structure for use in thinning semiconductor substrates and for supporting thinned semiconductor substrates 有权
标题翻译：用于减薄半导体衬底和用于支撑薄化半导体衬底的支撑结构
公开(公告)号：US07960829B2
公开(公告)日：2011-06-14
申请号：US11216617
申请日：2005-08-31
申请人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
发明人： Alan G. Wood , Warren M. Farnworth , David R. Hembree , Sidney B. Rigg , William M. Hiatt , Peter Benson , Kyle K. Kirby , Salman Akram
IPC分类号： H01L23/12
CPC分类号： G03F7/0037 , B33Y30/00 , B33Y70/00 , B33Y80/00 , G03F7/0047
摘要： A support structure for use with a semiconductor substrate in thinning, or backgrinding, thereof, as well as during post-thinning processing of the semiconductor substrate includes a portion that extends substantially along and around an outer periphery of the semiconductor substrate to impart the thinned semiconductor substrate with rigidity. The support structure may be configured as a ring or as a member that substantially covers an active surface of the semiconductor substrate and forms a protective structure over each semiconductor device carried by the active surface.
摘要翻译：用于半导体衬底的减薄或后研磨以及在半导体衬底的后变薄处理期间的支撑结构包括基本上沿着半导体衬底的外周延伸并围绕半导体衬底的外周延伸的部分，以使半导体衬底基板具有刚性。支撑结构可以被构造为环或作为基本上覆盖半导体衬底的有源表面并且在由有源表面承载的每个半导体器件上形成保护结构的构件。

4. 发明授权

US07956443B2 Through-wafer interconnects for photoimager and memory wafers 有权
标题翻译：用于光刻机和存储晶圆的透晶片互连
公开(公告)号：US07956443B2
公开(公告)日：2011-06-07
申请号：US12725724
申请日：2010-03-17
申请人： Salman Akram , Charles M. Watkins , Mark Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
发明人： Salman Akram , Charles M. Watkins , Mark Hiatt , David R. Hembree , James M. Wark , Warren M. Farnworth , Mark E. Tuttle , Sidney B. Rigg , Steven D. Oliver , Kyle K. Kirby , Alan G. Wood , Lu Velicky
IPC分类号： H01L23/485
CPC分类号： H01L21/76877 , H01L21/6835 , H01L21/76898 , H01L23/481 , H01L24/45 , H01L27/14634 , H01L27/14636 , H01L2221/6834 , H01L2224/02166 , H01L2224/0554 , H01L2224/05567 , H01L2224/05573 , H01L2224/16 , H01L2224/45144 , H01L2224/48463 , H01L2924/00014 , H01L2924/01013 , H01L2924/01014 , H01L2924/01028 , H01L2924/01029 , H01L2924/0105 , H01L2924/01078 , H01L2924/01079 , H01L2924/04941 , H01L2924/10253 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/05599 , H01L2224/0555 , H01L2224/0556
摘要： A through-wafer interconnect for imager, memory and other integrated circuit applications is disclosed, thereby eliminating the need for wire bonding, making devices incorporating such interconnects stackable and enabling wafer level packaging for imager devices. Further, a smaller and more reliable die package is achieved and circuit parasitics (e.g., L and R) are reduced due to the reduced signal path lengths.
摘要翻译：公开了一种用于成像器，存储器和其他集成电路应用的透晶片互连，从而消除了对引线接合的需要，使得结合这种互连的器件可堆叠并且实现成像器件的晶片级封装。此外，实现了更小且更可靠的管芯封装，并且由于信号路径长度的减小，电路寄生（例如，L和R）被减小。

5. 发明授权

US07919348B2 Methods for protecting imaging elements of photoimagers during back side processing 有权
标题翻译：用于在背面处理期间保护光成像器的成像元件的方法
公开(公告)号：US07919348B2
公开(公告)日：2011-04-05
申请号：US12139068
申请日：2008-06-13
申请人： Salman Akram , Kyle K. Kirby
发明人： Salman Akram , Kyle K. Kirby
IPC分类号： H01L21/00
CPC分类号： H01L27/14618 , H01L27/14636 , H01L27/14685 , H01L2224/13
摘要： Methods for processing photoimagers include forming one or more protective layers over the image sensing elements of a photoimager. Protective layers may facilitate thinning of the substrates of photoimagers, as well as prevent contamination of the image sensing elements and associated optical features during back side processing of the photoimagers. Blind vias, which extend from the back side of a photoimager to bond pads carried by an active surface of the photoimager, may be formed through the back side. The vias may be filled with conductive material and, optionally, redistribution circuitry may be fabricated over the back side of the photoimager. Photoimagers including features at result from such processes are also disclosed.
摘要翻译：用于处理光影目标的方法包括在光成像仪的图像感测元件上形成一个或多个保护层。保护层可以促进光刻胶的基材的变薄，并且可以防止在光成像器的背面处理期间图像感测元件和相关的光学特征的污染。可以通过背面形成从光电成像仪的背面延伸到由光电成像仪的有源表面承载的接合焊盘的盲通孔。通孔可以用导电材料填充，并且可选地，重新分布电路可以在光电成像仪的背面上制造。还公开了包括这些处理结果的特征的光照器。

6. 发明授权

US07855454B2 Semiconductor device structures including nickel plated aluminum, copper, and tungsten structures 有权
标题翻译：包括镀镍铝，铜和钨结构的半导体器件结构
公开(公告)号：US07855454B2
公开(公告)日：2010-12-21
申请号：US11702286
申请日：2007-02-05
申请人： Salman Akram , James M. Wark , William M. Hiatt
发明人： Salman Akram , James M. Wark , William M. Hiatt
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76879 , C23C18/1607 , C23C18/1637 , C23C18/1831 , C23C18/1834 , C23C18/34 , C23C18/36 , H01L21/288 , H01L21/76898 , H01L2924/00013 , Y10T428/12528 , Y10T428/24917 , H01L2224/29099
摘要： A method of activating a metal structure on an intermediate semiconductor device structure toward metal plating. The method comprises providing an intermediate semiconductor device structure comprising at least one first metal structure and at least one second metal structure on a semiconductor substrate. The at least one first metal structure comprises at least one aluminum structure, at least one copper structure, or at least one structure comprising a mixture of aluminum and copper and the at least one second metal structure comprises at least one tungsten structure. One of the at least one first metal structure and the at least one second metal structure is activated toward metal plating without activating the other of the at least one first metal structure and the at least one second metal structure. An intermediate semiconductor device structure is also disclosed.
摘要翻译：一种激活中间半导体器件结构上的金属结构朝向金属电镀的方法。该方法包括提供在半导体衬底上包括至少一个第一金属结构和至少一个第二金属结构的中间半导体器件结构。所述至少一个第一金属结构包括至少一个铝结构，至少一个铜结构或至少一个包括铝和铜的混合物的结构，并且所述至少一个第二金属结构包括至少一个钨结构。所述至少一个第一金属结构和所述至少一个第二金属结构中的一个被激活朝向金属镀覆，而不激活所述至少一个第一金属结构和所述至少一个第二金属结构中的另一个。还公开了一种中间半导体器件结构。

7. 发明授权

US07855140B2 Method of forming vias in semiconductor substrates and resulting structures 有权
标题翻译：在半导体衬底和结构中形成通孔的方法
公开(公告)号：US07855140B2
公开(公告)日：2010-12-21
申请号：US11781083
申请日：2007-07-20
申请人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
发明人： Charles M. Watkins , Kyle K. Kirby , Alan G. Wood , Salman Akram , Warren M. Farnworth
IPC分类号： H01L21/4763
CPC分类号： H01L21/76898
摘要： Methods for forming through vias in a semiconductor substrate and resulting structures are disclosed. In one embodiment, a through via may be formed by forming a partial via from an active surface through a conductive element thereon and a portion of the substrate underlying the conductive element. The through via may then be completed by laser ablation or drilling from a back surface. In another embodiment, a partial via may be formed by laser ablation or drilling from the back surface of a substrate to a predetermined distance therein. The through via may be completed from the active surface by forming a partial via extending through the conductive element and the underlying substrate to intersect the laser-drilled partial via. In another embodiment, a partial via may first be formed by laser ablation or drilling from the back surface of the substrate followed by dry etching to complete the through via.
摘要翻译：公开了在半导体衬底中形成贯通孔的方法和所得到的结构。在一个实施例中，可以通过从活性表面通过其上的导电元件和导电元件下面的基底的一部分形成部分通孔来形成通孔。然后可以通过从后表面的激光烧蚀或钻孔来完成通孔。在另一个实施例中，部分通孔可以通过激光烧蚀或从衬底的背面钻孔到其中的预定距离来形成。通孔可以通过形成延伸通过导电元件和下面的衬底以与激光钻孔的部分通孔相交的部分通孔从活性表面完成。在另一个实施例中，可以首先通过激光烧蚀或从衬底的背面进行钻孔形成部分通孔，然后通过干蚀刻来完成通孔。

8. 发明授权

US07759800B2 Microelectronics devices, having vias, and packaged microelectronic devices having vias 有权
标题翻译：具有通孔的微电子器件和具有通孔的封装的微电子器件
公开(公告)号：US07759800B2
公开(公告)日：2010-07-20
申请号：US11430735
申请日：2006-05-09
申请人： Sidney B. Rigg , Charles M. Watkins , Kyle K. Kirby , Peter A. Benson , Salman Akram
发明人： Sidney B. Rigg , Charles M. Watkins , Kyle K. Kirby , Peter A. Benson , Salman Akram
IPC分类号： H01L23/48 , H01L23/52 , H01L29/40
CPC分类号： H01L21/76898 , H01L23/481 , H01L24/48 , H01L25/0657 , H01L25/50 , H01L2224/48091 , H01L2224/48227 , H01L2225/06513 , H01L2225/06527 , H01L2225/06541 , H01L2924/00014 , H01L2924/01046 , H01L2924/01078 , H01L2924/04941 , H01L2924/12042 , H01L2924/14 , H01L2924/00 , H01L2224/45099 , H01L2224/45015 , H01L2924/207
摘要： Microelectronic devices, methods for packaging microelectronic devices, and methods for forming vias and conductive interconnects in microfeature workpieces and dies are disclosed herein. In one embodiment, a method includes forming a bond-pad on a die having an integrated circuit, the bond-pad being electrically coupled to the integrated circuit. A conductive line is then formed on the die, the conductive line having a first end portion attached to the bond-pad and a second end portion spaced apart from the bond-pad. The method can further include forming a via or passage through the die, the bond-pad, and the first end portion of the conductive line, and depositing an electrically conductive material in at least a portion of the passage to form a conductive interconnect extending at least generally through the microelectronic device.
摘要翻译：本文公开了微电子器件，用于封装微电子器件的方法，以及用于在微特征工件和管芯中形成通路和导电互连的方法。在一个实施例中，一种方法包括在具有集成电路的管芯上形成接合焊盘，所述接合焊盘电耦合到集成电路。然后在管芯上形成导线，导电线具有附接到接合焊盘的第一端部和与接合焊盘间隔开的第二端部。该方法还可以包括形成通过管芯，接合焊盘和导电线的第一端部的通孔或通道，以及在通道的至少一部分中沉积导电材料以形成延伸在最不通常地通过微电子器件。

9. 发明授权

US07759240B2 Use of palladium in IC manufacturing with conductive polymer bump 失效
标题翻译：在导电聚合物凸块的IC制造中使用钯
公开(公告)号：US07759240B2
公开(公告)日：2010-07-20
申请号：US12024712
申请日：2008-02-01
申请人： Warren M. Farnworth , Salman Akram
发明人： Warren M. Farnworth , Salman Akram
IPC分类号： H01L21/44
CPC分类号： H05K3/321 , H01L21/288 , H01L21/4853 , H01L21/563 , H01L23/49811 , H01L23/49816 , H01L23/49894 , H01L24/29 , H01L24/81 , H01L24/83 , H01L2224/11 , H01L2224/1132 , H01L2224/12 , H01L2224/13099 , H01L2224/1319 , H01L2224/16 , H01L2224/16225 , H01L2224/2919 , H01L2224/29298 , H01L2224/73203 , H01L2224/73204 , H01L2224/81801 , H01L2224/838 , H01L2924/00013 , H01L2924/01005 , H01L2924/01013 , H01L2924/01029 , H01L2924/01033 , H01L2924/01046 , H01L2924/01047 , H01L2924/0105 , H01L2924/01074 , H01L2924/01078 , H01L2924/01079 , H01L2924/01082 , H01L2924/014 , H01L2924/0665 , H01L2924/0781 , H01L2924/12044 , H01L2924/14 , H05K3/244 , H05K2201/10674 , H05K2201/10977 , H05K2201/10984 , H01L2924/00 , H01L2924/3512 , H01L2924/00014 , H01L2224/29099 , H01L2224/29199 , H01L2224/29299 , H01L2224/2929 , H01L2924/00012
摘要： An apparatus and a method for forming a substrate having a palladium metal layer over at least one contact point of the substrate and having a flexible conductive polymer bump, preferably a two-stage epoxy, on the palladium plated contact point, are provided. The present invention also relates to assemblies comprising one or more of these substrates.
摘要翻译：提供了一种用于在镀钯触点上形成具有钯金属层的衬底的方法，该衬底在衬底的至少一个接触点上并具有柔性导电聚合物凸块，优选两级环氧树脂。本发明还涉及包括一个或多个这些基底的组件。

10. 发明授权

US07709279B2 Methods for testing semiconductor devices methods for protecting the same from electrostatic discharge events during testing, and methods for fabricating inserts for use in testing semiconductor devices 有权
标题翻译：用于测试半导体器件的方法，用于在测试期间保护其免受静电放电事件的方法，以及用于制造用于测试半导体器件的插入件的方法
公开(公告)号：US07709279B2
公开(公告)日：2010-05-04
申请号：US10827806
申请日：2004-04-20
申请人： David R. Hembree , Salman Akram
发明人： David R. Hembree , Salman Akram
IPC分类号： H01L21/66 , H01L23/58
CPC分类号： G01R1/18 , H01L22/34 , H01L23/5256 , H01L27/0251 , H01L2924/0002 , H01L2924/00
摘要： An apparatus and method for providing external electrostatic discharge (ESD) protection to a semiconductor device, which may or may not include its own ESD protection, are provided. An ESD structure may be associated with each interconnect, either individually or shared between two or more interconnects. Each interconnect includes a contact tip for establishing a temporary electrical connection with a bond pad of the semiconductor device and a contact pad for electrically interfacing the bond pad with external burn-in and/or test equipment. The ESD structure may be implemented, for example, as a fusible element or a shunting element, such as a pair of diodes, a diode-resistor network, or a pair of transistors. The interconnect may be employed as part of an insert including a plurality of interconnects that provides ESD protection to a plurality of integrated circuits of at least one semiconductor device.
摘要翻译：提供了一种用于向半导体器件提供外部静电放电（ESD）保护的装置和方法，其可以包括或可以不包括其自身的ESD保护。 ESD结构可以与每个互连相关联，单独地或在两个或更多个互连之间共享。每个互连包括用于与半导体器件的接合焊盘建立临时电连接的接触尖端和用于将接合焊盘与外部老化和/或测试设备电接口的接触焊盘。 ESD结构可以实现为例如可熔元件或分流元件，例如一对二极管，二极管 - 电阻器网络或一对晶体管。互连可以用作插入件的一部分，其包括向至少一个半导体器件的多个集成电路提供ESD保护的多个互连。

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