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41. 发明申请

US20220383444A1 GENERATION AND STORAGE OF COMPRESSED Z-PLANES IN GRAPHICS PROCESSING 有权
公开(公告)号：US20220383444A1
公开(公告)日：2022-12-01
申请号：US17332596
申请日：2021-05-27
申请人： Intel Corporation
发明人： Saikat Mandal , Karol Szerszen , Vasanth Ranganathan , Altug Koker , Michael Norris , Prasoonkumar Surti , Takahiro Murata
IPC分类号： G06T1/20 , G06T1/60 , G06T15/00
摘要： Generation and storage of compressed z-planes in graphics processing is described. An example of a processor includes a rasterizer to generate a fragment of pixel data including blocks of pixel data; a depth pipeline to receive the fragment, the pipeline including a first and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining minimum and maximum depths for each block; and a depth buffer, wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes a first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.

42. 发明申请

US20220375023A1 SYSTEMS AND METHODS TO PROCESS ELECTRONIC IMAGES TO PROVIDE IMPROVED VISUALIZATION AND RENDERING OF HISTOPATHOLOGY SLIDES 有权
公开(公告)号：US20220375023A1
公开(公告)日：2022-11-24
申请号：US17880766
申请日：2022-08-04
申请人： PAIGE.AI, Inc.
发明人： Alexandre KIRSZENBERG , Razik YOUSFI , Thomas FRESNEAU , Peter SCHUEFFLER
IPC分类号： G06T1/60 , G06V20/69 , G06T7/00 , H04N5/225 , H04N5/232
摘要： A method for processing an electronic image including receiving, by a viewer, the electronic image and a FOV (field of view), wherein the FOV includes at least one coordinate, at least one dimension, and a magnification factor, loading, by the viewer, a plurality of tiles within the FOV, determining, by the viewer, a state of the plurality of tiles in a cache, and in response to determining that the state of the plurality of tiles in the cache is a fully loaded state, rendering, by the viewer, the plurality of tiles to a display.

43. 发明授权

US11507375B2 Hierarchical general register file (GRF) for execution block 有权
公开(公告)号：US11507375B2
公开(公告)日：2022-11-22
申请号：US17319056
申请日：2021-05-12
申请人： Intel Corporation
发明人： Abhishek R. Appu , Altug Koker , Joydeep Ray , Kamal Sinha , Kiran C. Veernapu , Subramaniam Maiyuran , Prasoonkumar Surti , Guei-Yuan Lueh , David Puffer , Supratim Pal , Eric J. Hoekstra , Travis T. Schluessler , Linda L. Hurd
IPC分类号： G06F9/30 , G06T15/00 , G06T1/60 , G06T1/20 , G06F9/46 , G09G5/36 , G06F9/38
摘要： In an example, an apparatus comprises a plurality of execution units, and a first general register file (GRF) communicatively couple to the plurality of execution units, wherein the first GRF is shared by the plurality of execution units. Other embodiments are also disclosed and claimed.

44. 发明授权

US11495191B2 Reading extended display identification data (EDID) from display device to get native resolution of display device 有权
公开(公告)号：US11495191B2
公开(公告)日：2022-11-08
申请号：US16706794
申请日：2019-12-08
申请人： Wistron Corporation
发明人： Feng-Yuan Chen , Chou-Chieh Chang
IPC分类号： G09G5/00 , G06T1/60
摘要： A display device, an electronic system and a control method are disclosed. The display device includes a memory device. The memory device includes a memory array, an input/output logic circuit and a control logic circuit. The memory array includes a plurality of sub-arrays and each sub-array stores extended display identification data. The input/output logic circuit is configured to receive an identification data request from a host device and determine whether to perform an identification data access process according to the identification data request The control logic circuit is configured to read extended display identification data stored in a target sub-array of the plurality of sub-arrays of the memory array according to memory address information in response to determining to perform the identification data access process.

45. 发明申请

US20220351426A1 CONTROLLING INTERACTIVITY OF DIGITAL CONTENT OVERLAID ONTO DISPLAYED DATA VIA GRAPHICS PROCESSING CIRCUITRY USING A FRAME BUFFER 有权
公开(公告)号：US20220351426A1
公开(公告)日：2022-11-03
申请号：US17675950
申请日：2022-02-18
申请人： Mobeus Industries, Inc.
发明人： Dharmendra ETWARU , Michael R. SUTCLIFF , Aram ANDRIASYAN
IPC分类号： G06T11/00 , G06T1/60 , G06T7/73 , G06F3/04883
摘要： An apparatus, method, and computer readable medium that access a frame buffer of a graphics processing unit (GPU), analyze, in the frame buffer, a frame representing displayed data, based on the analyzed frame, identify a reference patch that includes an instruction to retrieve content, generate an overlay including an augmentation layer which includes the content, superimpose the overlay onto the displayed data such that the content is viewable while a portion of the base layer is obscured, detect a user input, determine a location of the user input in the augmentation layer, associate the location in the augmentation layer with a target location in the base layer, and associate, within memory, the target location with an operation such that the user input in the augmentation layer activates an input in the base layer.

46. 发明申请

US20220345624A1 IMAGE SENSOR MODULE AND METHOD OF OPERATING THE SAME 有权
公开(公告)号：US20220345624A1
公开(公告)日：2022-10-27
申请号：US17727055
申请日：2022-04-22
申请人： Samsung Electronics Co., Ltd.
发明人： Kyoungyoung KIM , Sangsoo KO , Byeoungsu KIM , Sanghyuck HA
IPC分类号： H04N5/232 , G06T7/11 , G06T7/12 , G06T1/20 , G06T1/60
摘要： An image sensor module includes an image sensor configured to generate image data; a memory including a processor in memory (PIM) circuit, of the PIM circuit including banks configured to store the image data and a plurality of processing elements; and a signal processor, wherein the memory is configured to read the image data from the banks, perform a first image processing operation on the image data by using the processing elements corresponding to the banks, and store image-processed image data on which the first image processing operation is performed in the banks or output the image-processed image data.

47. 发明申请

US20220343554A1 CONTEXT-AWARE COMPRESSION WITH QUANTIZATION OF HIERARCHICAL TRANSFORM MATRICES 有权
公开(公告)号：US20220343554A1
公开(公告)日：2022-10-27
申请号：US17740754
申请日：2022-05-10
申请人： INTEL CORPORATION
发明人： Carson BROWNLEE , Carsten BENTHIN , Joshua BARCZAK , Kai XIAO , Michael APODACA , Prasoonkumar SURTI , Thomas RAOUX
IPC分类号： G06T9/40 , G06T15/06 , G06T15/20 , G06T1/60
摘要： Apparatus and method for context-aware compression. For example, one embodiment of an apparatus comprises: ray traversal/intersection circuitry to traverse rays through a hierarchical acceleration data structure to identify intersections between rays and primitives of a graphics scene; matrix compression circuitry/logic to compress hierarchical transformation matrices to generate compressed hierarchical transformation matrices by quantizing N-bit floating point data elements associated with child transforms of the hierarchical transformation matrices to variable-bit floating point numbers or integers comprising offsets from a parent transform of the child transform; and an instance processor to generate a plurality of instances of one or more base geometric objects in accordance with the compressed hierarchical transformation matrices.

48. 发明授权

US11481976B2 Instruction list generation 有权
公开(公告)号：US11481976B2
公开(公告)日：2022-10-25
申请号：US17269049
申请日：2018-11-27
申请人： RENESAS ELECTRONICS CORPORATION
发明人： Bjoern Toschi
IPC分类号： G06T17/20 , G06T1/60 , G06K9/62 , G06V10/75
摘要： A system for and a method of generating an ordered list of instructions comprising a list of pixel coordinates which are vertices of triangles in a strip of a reference input image in a source coordinate system such that transformation of the vertices to a corresponding output image in a destination coordinate system causes the triangles to be mapped to a block of image data which maps to a block of line memory (or “texture cache”). The method comprises dividing the reference output image into a plurality of tiled sections in the destination coordinate system. The method comprises, for each section, defining first and second boundaries of an array of strips of pixels in the section by dividing the section into blocks of line memory. The method comprises, for each strip, dividing each set of pixels contained in each strip into a series of ordered triangles, generating a set of destination and source coordinates for each vertex of each triangle in the strip and storing the coordinates of the vertices in source and destination coordinate system, in the ordered list of instructions.

49. 发明授权

US11481939B2 Systems and methods for 3D data visualization and network extraction 有权
公开(公告)号：US11481939B2
公开(公告)日：2022-10-25
申请号：US17157819
申请日：2021-01-25
申请人： Virtualities, Inc.
发明人： Aakash Indurkhya , Ciro Donalek , Michael Amori , Sarthak Sahu , Vaibhav Anand , Justin Gantenberg
IPC分类号： G06T11/20 , G06T1/60 , G06F16/904 , G06F16/901 , G06T1/20
摘要： Systems and methods for data visualization and network extraction in accordance with embodiments of the invention are illustrated. One embodiment includes a method including obtaining a graph comprising a plurality of nodes and a plurality of edges, identifying a plurality of communities in the graph, where each community includes nodes from the plurality of nodes, generating a community graph structure based on the identified communities, where the community graph includes a plurality of supernodes and a plurality of superedges, spatializing the community graph structure, unpacking the spatialized community graph structure into an unpacked graph structure comprising the plurality of nodes and the plurality of edges, where each node in the plurality of nodes is located at approximately the position of the supernode that represented it, spatializing the unpacked graph structure, and providing the spatialized unpacked graph structure.

50. 发明授权

US11475623B2 Apparatus and method for efficient graphics virtualization 有权
公开(公告)号：US11475623B2
公开(公告)日：2022-10-18
申请号：US17141431
申请日：2021-01-05
申请人： Intel Corporation
发明人： Joydeep Ray , Abhishek R. Appu , Pattabhiraman K , Balaji Vembu , Altug Koker , Niranjan L. Cooray , Josh B. Mastronarde
IPC分类号： G06T15/00 , G06F9/455 , G06T1/60 , G09G5/36 , G09G5/00 , G09G5/393 , G06F9/48 , G06F9/50 , G06T15/04 , G06T15/80 , G06T17/10 , G06T17/20
摘要： An apparatus and method are described for allocating local memories to virtual machines. For example, one embodiment of an apparatus comprises: a command streamer to queue commands from a plurality of virtual machines (VMs) or applications, the commands to be distributed from the command streamer and executed by graphics processing resources of a graphics processing unit (GPU); a tile cache to store graphics data associated with the plurality of VMs or applications as the commands are executed by the graphics processing resources; and tile cache allocation hardware logic to allocate a first portion of the tile cache to a first VM or application and a second portion of the tile cache to a second VM or application; the tile cache allocation hardware logic to further allocate a first region in system memory to store spill-over data when the first portion of the tile cache and/or the second portion of the file cache becomes full.

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