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1. 发明授权

US11087522B1 Apparatus and method for asynchronous ray tracing 有权
公开(公告)号：US11087522B1
公开(公告)日：2021-08-10
申请号：US16819121
申请日：2020-03-15
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Abhishek R. Appu , Karthik Vaidyanathan , Saikat Mandal , Michael Norris
IPC分类号： G06T15/00 , G06F3/06 , G06T15/06
摘要： Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the BVH; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the BVH by reading a next BVH node from a top of a BVH node stack and determining whether the next ray intersects the next BVH node.

2. 发明公开

US20240257433A1 APPARATUS AND METHOD FOR ASYNCHRONOUS RAY TRACING 审中-公开
公开(公告)号：US20240257433A1
公开(公告)日：2024-08-01
申请号：US18414841
申请日：2024-01-17
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Abhishek R. Appu , Karthik Vaidyanathan , Saikat Mandal , Michael Norris
IPC分类号： G06T15/00 , G06F3/06 , G06T15/06
CPC分类号： G06T15/005 , G06F3/0604 , G06F3/0659 , G06F3/0673 , G06T15/06
摘要： Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the BVH; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the BVH by reading a next BVH node from a top of a BVH node stack and determining whether the next ray intersects the next BVH node.

3. 发明申请

US20220383444A1 GENERATION AND STORAGE OF COMPRESSED Z-PLANES IN GRAPHICS PROCESSING 有权
公开(公告)号：US20220383444A1
公开(公告)日：2022-12-01
申请号：US17332596
申请日：2021-05-27
申请人： Intel Corporation
发明人： Saikat Mandal , Karol Szerszen , Vasanth Ranganathan , Altug Koker , Michael Norris , Prasoonkumar Surti , Takahiro Murata
IPC分类号： G06T1/20 , G06T1/60 , G06T15/00
摘要： Generation and storage of compressed z-planes in graphics processing is described. An example of a processor includes a rasterizer to generate a fragment of pixel data including blocks of pixel data; a depth pipeline to receive the fragment, the pipeline including a first and second depth test hardware, the first depth test hardware to perform a coarse depth test including determining minimum and maximum depths for each block; and a depth buffer, wherein the processor is to determine whether the fragment meets requirements that the fragment fully covers a tile of pixel data and passes a first depth test, and that each of the minimum and maximum depths of the fragment has a same sign and exponent, and, upon determining that the fragment meets the requirements, to generate a compressed depth plane utilizing the first depth test and update the depth buffer with the compressed depth plane.

4. 发明申请

US20220130097A1 APPARATUS AND METHOD FOR ASYNCHRONOUS RAY TRACING 有权
公开(公告)号：US20220130097A1
公开(公告)日：2022-04-28
申请号：US17392810
申请日：2021-08-03
申请人： Intel Corporation
发明人： Prasoonkumar Surti , Abhishek R. Appu , Karthik Vaidyanathan , Saikat Mandal , Michael Norris
IPC分类号： G06T15/00 , G06F3/06 , G06T15/06
摘要： Apparatus and method for asynchronous ray tracing. For example, one embodiment of a processor comprises: a bounding volume hierarchy (BVH) generator to construct a BVH comprising a plurality of hierarchically arranged nodes including a root node, a plurality of internal nodes, and a plurality of leaf nodes comprising primitives, wherein each internal node comprises a child node to either the root node or another internal node and each leaf node comprises a child node to an internal node; a first storage bank to be arranged as a first plurality of entries; a second storage bank to be arranged as a second plurality of entries, wherein each entry of the first plurality of entries and the second plurality of entries is to store a ray to be traversed through the BVH; an allocator circuit to distribute an incoming ray to either the first storage bank or the second storage bank based on a relative numbers of rays currently stored in the first and second storage banks; and traversal circuitry to alternate between selecting a next ray from the first storage bank and the second storage bank, the traversal circuitry to traverse the next ray through the BVH by reading a next BVH node from a top of a BVH node stack and determining whether the next ray intersects the next BVH node.

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