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41. 发明授权

US09208840B2 Semiconductor memory device having an electrically floating body transistor 有权
标题翻译：具有电浮体晶体管的半导体存储器件
公开(公告)号：US09208840B2
公开(公告)日：2015-12-08
申请号：US14330083
申请日：2014-07-14
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja , Zvi Or-Bach
IPC分类号： G11C7/22 , G11C11/404 , H01L27/108 , H01L29/78 , H01L29/772 , G11C11/04
CPC分类号： H01L27/10802 , G11C7/22 , G11C11/04 , G11C11/39 , G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C14/0018 , G11C2211/4016 , H01L23/528 , H01L29/1095 , H01L29/66825 , H01L29/66833 , H01L29/772 , H01L29/7841 , H01L29/7881
摘要： A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.
摘要翻译：一种用于对具有行和列的存储器单元的半导体存储器阵列进行保持操作的方法，包括：将电信号施加到存储器单元的掩埋区域，其中每个存储器单元包括限定至少一部分的浮体区域所述浮体区域具有第一导电类型; 并且其中每个存储单元的所述埋入区位于所述存储单元内并且位于所述浮体区附近，所述掩埋区具有第二导电类型。

42. 发明授权

US09190320B2 Devices including metal-silicon contacts using indium arsenide films and apparatus and methods 有权
标题翻译：包括使用砷化铟膜的金属 - 硅触点的装置和装置和方法
公开(公告)号：US09190320B2
公开(公告)日：2015-11-17
申请号：US13748910
申请日：2013-01-24
申请人： Applied Materials, Inc.
发明人： Khaled Z. Ahmed , Prabu Gopalraja , Atif Noori , Mei Chang
IPC分类号： H01L21/44 , H01L21/768 , H01L21/67 , H01L23/482 , H01L29/772 , H01L21/285
CPC分类号： C23C16/52 , C23C14/22 , C23C16/0227 , C23C16/45544 , H01L21/28525 , H01L21/6715 , H01L21/6719 , H01L21/67207 , H01L21/76843 , H01L23/4827 , H01L29/772 , H01L2924/0002 , H01L2924/00
摘要： Described are apparatus and methods for forming films comprise indium and arsenic. In particular, these films may be formed in a configuration of two or more chambers under “load lock” conditions. These films may include additional components as dopants, such as aluminum and/or gallium. Such films can be used in metal/silicon contacts having low contact resistances. Also disclosed are devices including the films comprising indium arsenide.
摘要翻译：描述了用于形成薄膜的装置和方法包括铟和砷。特别地，这些膜可以在“负载锁定”条件下形成为两个或更多个室的构造。这些膜可以包括作为掺杂剂的附加组分，例如铝和/或镓。这种膜可以用于具有低接触电阻的金属/硅触点。还公开了包括包含砷化铟的膜的装置。

43. 发明申请

US20150311149A1 SEMICONDUCTOR DEVICE WITH COMBINED PASSIVE DEVICE ON CHIP BACK SIDE 审中-公开
公开(公告)号：US20150311149A1
公开(公告)日：2015-10-29
申请号：US14791051
申请日：2015-07-02
申请人： Infineon Technologies Austria AG
发明人： Andreas Munding , Martin Gruber
IPC分类号： H01L23/498 , H01L49/02 , H01L29/772 , H01L33/00 , H01L33/48 , H01L27/06 , H01L23/495 , H01L27/15 , H01L33/38 , H01L21/283 , H01L21/52
CPC分类号： H01L23/49838 , H01L21/283 , H01L21/52 , H01L23/49541 , H01L23/642 , H01L25/16 , H01L25/167 , H01L27/0629 , H01L27/0694 , H01L27/15 , H01L28/40 , H01L28/60 , H01L29/772 , H01L33/005 , H01L33/38 , H01L33/483 , H01L2224/06181 , H01L2924/1305 , H01L2924/1306 , H01L2924/13091 , H01L2924/14 , H01L2924/1431 , H01L2924/19041 , H01L2924/19042 , H01L2924/19043 , H01L2924/19103 , H01L2933/0016 , H01L2933/0033 , H01L2924/00
摘要： Semiconductor chips are described that combine a semiconductor device and a capacitor onto a single substrate such that the semiconductor device and the capacitor are electrically isolated from each other. In one example, a semiconductor chip includes a substrate having a first side and a second side, wherein the second side is opposite the first side. The semiconductor chip further includes a semiconductor device formed on the first side of the substrate and an electrically insulating layer formed on at least a portion of the second side of the substrate. The semiconductor chip further includes a capacitor device formed on at least a portion of the electrically insulating layer on the second side of the substrate, wherein the capacitor device is electrically insulated from the semiconductor device.

44. 发明授权

US09136366B2 Transistor with coupled gate and ground plane 有权
标题翻译：具有耦合栅极和接地层的晶体管
公开(公告)号：US09136366B2
公开(公告)日：2015-09-15
申请号：US14156559
申请日：2014-01-16
申请人： Commissariat a l'energie atomique et aux energies alternatives , STMicroelectronics SA
发明人： Bastien Giraud , Jean-Philippe Noel , Maud Vinet
IPC分类号： H01L29/66 , H01L29/78 , H01L29/423 , H01L29/772 , H01L29/786
CPC分类号： H01L29/78 , H01L29/42392 , H01L29/66575 , H01L29/785 , H01L29/7855 , H01L29/7856 , H01L29/78696
摘要： An integrated circuit includes a silicon substrate, a ground plane above the substrate, a buried insulator layer above the ground plane, a silicon layer above the buried insulator layer and separated from the ground plane by the buried insulator layer, and an FDSOI transistor. The transistor has a channel adapted for being formed in the silicon layer, a source and drain in and/or on the silicon layer, and a gate covering an upper face of the channel and having a lateral portion covering a lateral face of the channel and above the ground plane. A distance between the lateral portion and the ground plane is not more than three nanometers and at least five times less than a thickness of the buried insulator layer between the ground plane and the silicon layer. The ground plane is separated from the gate by the buried insulator layer.
摘要翻译：集成电路包括硅衬底，衬底上方的接地平面，接地平面上方的掩埋绝缘体层，掩埋绝缘体层上方的硅层，并由掩埋绝缘体层与接地层分离，以及FDSOI晶体管。晶体管具有适于在硅层中形成的沟道，硅层中和/或硅层上的源极和漏极，以及覆盖沟道的上表面的栅极，并且具有覆盖沟道的侧面的侧面部分，以及在地面以上。横向部分和接地面之间的距离不大于接地平面和硅层之间的掩埋绝缘体层的厚度的三纳米至少五倍。接地层由掩埋绝缘体层与栅极分离。

45. 发明授权

US09123562B2 Layout method to minimize context effects and die area 有权
标题翻译：布局方法，尽量减少上下文影响和模具面积
公开(公告)号：US09123562B2
公开(公告)日：2015-09-01
申请号：US13622925
申请日：2012-09-19
申请人： Texas Instruments Incorporated
发明人： James Walter Blatchford , Thomas J. Aton
IPC分类号： H01L27/088 , H01L29/772 , H01L21/8234 , H01L27/02 , H01L29/78
CPC分类号： H01L27/0207 , H01L21/823412 , H01L21/823418 , H01L21/823425 , H01L21/823437 , H01L27/088 , H01L29/78 , H01L2924/10157
摘要： An integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region and where a gate overlies said jog. A method of making an integrated circuit with an active geometry with a wide active region and with a narrow active region with at least one jog where said wide active region transitions to said narrow active region, where a gate overlies said jog and where a gate overlies the wide active region forming a wide transistor.
摘要翻译：一种具有有源几何形状的集成电路，其具有宽的有源区和具有至少一个点的窄有源区，其中所述宽有源区转变到所述窄有源区，并且栅极覆盖所述点动。一种制造具有有源几何形状的集成电路的方法，其具有宽的有源区和具有至少一个点的窄有源区，其中所述宽有源区转变到所述窄有源区，其中栅极覆盖所述点动，并且栅极覆盖形成宽晶体管的宽有源区。

46. 发明授权

US09099552B2 Semiconductor device and method of manufacturing the same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09099552B2
公开(公告)日：2015-08-04
申请号：US14187871
申请日：2014-02-24
申请人： Semiconductor Components Industries, LLC
发明人： Yasuhiro Takeda , Shinya Inoue , Yuzo Otsuru
IPC分类号： H01L29/772 , H01L29/78 , H01L29/10 , H01L29/66 , H01L29/08 , H01L29/423 , H01L29/45 , H01L29/49
CPC分类号： H01L29/7816 , H01L29/086 , H01L29/0878 , H01L29/1083 , H01L29/1095 , H01L29/42368 , H01L29/456 , H01L29/4933 , H01L29/66689
摘要： The invention provides an LDMOS transistor of which the time-dependent degrading of the performance due to the trapping of hot electrons in the gate insulation film is decreased. A body layer is disposed in a surface portion of an N− type semiconductor layer. A source layer including an N− type layer is disposed in a surface portion of the body layer. An N− type drift layer is formed in a surface portion of the N− type semiconductor layer. This drift layer includes a first region having a first N type impurity concentration peak region and a second region having a second N type impurity concentration peak region that is positioned deeper than the first N type impurity concentration peak region, the second region adjoining this first region. An N+ type drain layer is formed in a surface portion of the second region.
摘要翻译：本发明提供了一种LDMOS晶体管，其中由于在栅极绝缘膜中捕获热电子而导致的性能的时间依赖性降低。主体层设置在N-型半导体层的表面部分中。包括N型层的源极层设置在主体层的表面部分中。在N-型半导体层的表面部分形成有N型漂移层。该漂移层包括具有第一N型杂质浓度峰值区域的第一区域和位于比第一N型杂质浓度峰值区域更深的第二N型杂质浓度峰值区域的第二区域，与该第一区域相邻的第二区域。在第二区域的表面部分中形成N +型漏极层。

47. 发明授权

US09082641B2 Semiconductor device with contact hole and manufacturing method thereof 有权
标题翻译：具有接触孔的半导体器件及其制造方法
公开(公告)号：US09082641B2
公开(公告)日：2015-07-14
申请号：US13897836
申请日：2013-05-20
申请人： Semiconductor Manufacturing International Corporation (Shanghai)
发明人： James Hong
IPC分类号： H01L29/772 , H01L27/088 , H01L29/66 , H01L21/8234 , H01L29/49
CPC分类号： H01L27/088 , H01L21/82345 , H01L29/4966 , H01L29/66477 , H01L29/66545
摘要： A semiconductor device includes a substrate, a first barrier layer disposed on the substrate, a first dielectric layer disposed on the first barrier layer, and a second barrier layer disposed on the first barrier layer. The semiconductor device further includes a third barrier layer and a first metal gate each being disposed between a first portion of the second barrier layer and a second portion of the second barrier layer. The first metal gate is disposed between the third barrier layer and the substrate. The semiconductor device further includes a second dielectric layer. The third barrier layer is disposed between the first metal gate and the second dielectric layer. The semiconductor device further includes a second metal gate. The semiconductor device further includes a contact hole positioned between the first metal gate and the second metal gate.
摘要翻译：半导体器件包括衬底，设置在衬底上的第一势垒层，设置在第一阻挡层上的第一电介质层和设置在第一阻挡层上的第二势垒层。半导体器件还包括第三阻挡层和第一金属栅极，每个第一栅极层和第一金属栅极分别设置在第二阻挡层的第一部分和第二阻挡层的第二部分之间。第一金属栅极设置在第三阻挡层和基板之间。半导体器件还包括第二介电层。第三阻挡层设置在第一金属栅极和第二电介质层之间。半导体器件还包括第二金属栅极。半导体器件还包括位于第一金属栅极和第二金属栅极之间的接触孔。

48. 发明授权

US09054172B2 Semiconductor structure having contact plug and method of making the same 有权
标题翻译：具有接触塞的半导体结构及其制造方法
公开(公告)号：US09054172B2
公开(公告)日：2015-06-09
申请号：US13705175
申请日：2012-12-05
申请人： UNITED MICROELECTRNICS CORP.
发明人： Ching-Wen Hung , Chih-Sen Huang , Po-Chao Tsao , Chieh-Te Chen
IPC分类号： H01L29/772 , H01L29/78 , H01L21/768 , H01L23/485 , H01L29/417 , H01L23/532 , H01L29/66 , H01L29/165
CPC分类号： H01L21/76897 , H01L21/283 , H01L21/32115 , H01L21/76816 , H01L21/76877 , H01L23/485 , H01L23/528 , H01L23/53209 , H01L23/53223 , H01L23/53238 , H01L23/53266 , H01L23/53295 , H01L29/165 , H01L29/41725 , H01L29/41758 , H01L29/41783 , H01L29/45 , H01L29/665 , H01L29/66545 , H01L29/66575 , H01L29/78 , H01L29/7843 , H01L29/7845 , H01L29/7848 , H01L2924/0002 , H01L2924/00
摘要： The present invention provides a semiconductor structure including a substrate, a transistor, a first ILD layer, a second ILD layer, a first contact plug, second contact plug and a third contact plug. The transistor is disposed on the substrate and includes a gate and a source/drain region. The first ILD layer is disposed on the transistor. The first contact plug is disposed in the first ILD layer and a top surface of the first contact plug is higher than a top surface of the gate. The second ILD layer is disposed on the first ILD layer. The second contact plug is disposed in the second ILD layer and electrically connected to the first contact plug. The third contact plug is disposed in the first ILD layer and the second ILD layer and electrically connected to the gate. The present invention further provides a method of making the same.
摘要翻译：本发明提供了一种半导体结构，其包括衬底，晶体管，第一ILD层，第二ILD层，第一接触插塞，第二接触插塞和第三接触插塞。晶体管设置在衬底上并且包括栅极和源极/漏极区域。第一ILD层设置在晶体管上。第一接触插塞设置在第一ILD层中，并且第一接触插塞的顶表面高于栅极的顶表面。第二ILD层设置在第一ILD层上。第二接触插塞设置在第二ILD层中并电连接到第一接触插塞。第三接触插塞设置在第一ILD层和第二ILD层中并且电连接到栅极。本发明还提供了制备该方法的方法。

49. 发明授权

US09041103B2 RESURF semiconductor device charge balancing 有权
标题翻译： RESURF半导体器件电荷平衡
公开(公告)号：US09041103B2
公开(公告)日：2015-05-26
申请号：US13781722
申请日：2013-02-28
申请人： Won Gi Min , Zhihong Zhang , Hongzhong Xu , Jiang-Kai Zuo
发明人： Won Gi Min , Zhihong Zhang , Hongzhong Xu , Jiang-Kai Zuo
IPC分类号： H01L29/772 , H01L29/78 , H01L29/06 , H01L29/08 , H01L29/10
CPC分类号： H01L29/7823 , H01L29/063 , H01L29/0634 , H01L29/0653 , H01L29/0692 , H01L29/0847 , H01L29/0882 , H01L29/1083 , H01L29/1087 , H01L29/1095 , H01L29/7816 , H01L29/7835 , H01L2924/0002 , H01L2924/00
摘要： Breakdown voltage BVdss is enhanced and ON-resistance reduced in RESURF devices, e.g., LDMOS transistors, by careful charge balancing, even when body and drift region charge balance is not ideal, by: (i) providing a plug or sinker near the drain and of the same conductivity type extending through the drift region at least into the underlying body region, and/or (ii) applying bias Viso to a surrounding lateral doped isolation wall coupled to the device buried layer, and/or (iii) providing a variable resistance bridge between the isolation wall and the drift region. The bridge may be a FET whose source-drain couple the isolation wall and drift region and whose gate receives control voltage Vc, or a resistor whose cross-section (X, Y, Z) affects its resistance and pinch-off, to set the percentage of drain voltage coupled to the buried layer via the isolation wall.
摘要翻译：即使在身体和漂移区域电荷平衡不理想的情况下，即使在（i）在漏极附近提供插头或沉降片，即使通过仔细的电荷平衡，RESURF器件（例如LDMOS晶体管）中的击穿电压BVdss也能够降低导通电阻，和/或（ii）将偏置Viso施加到耦合到器件掩埋层的周围横向掺杂隔离壁，和/或（iii）提供可变的隔离墙和漂移区之间的电阻桥。该桥可以是FET，其漏极耦合隔离壁和漂移区，并且其栅极接收控制电压Vc，或者其截面（X，Y，Z）影响其电阻和夹断的电阻器，以设置通过隔离壁耦合到掩埋层的漏极电压的百分比。

50. 发明授权

US09041056B2 Semiconductor device and method of manufacturing same 有权
标题翻译：半导体装置及其制造方法
公开(公告)号：US09041056B2
公开(公告)日：2015-05-26
申请号：US13346906
申请日：2012-01-10
申请人： Toshitaka Miyata , Kanna Adachi , Shigeru Kawanaka
发明人： Toshitaka Miyata , Kanna Adachi , Shigeru Kawanaka
IPC分类号： H01L29/16 , H01L29/772 , H01L29/08 , H01L29/10 , H01L29/78 , H01L29/165 , H01L29/66
CPC分类号： H01L29/772 , H01L29/0895 , H01L29/1054 , H01L29/1608 , H01L29/165 , H01L29/6656 , H01L29/7836
摘要： According to one embodiment, a semiconductor device including: a substrate; a gate electrode formed above the substrate; a gate insulating film formed under the gate electrode; a channel layer formed under the gate insulating film by using a channel layer material; a source region and a drain region formed in the substrate so as to interpose the channel layer therebetween in a channel direction; and a source extension layer formed in the substrate between the channel layer and the source region so as to overlap a source-side end portion of the channel layer. The source extension layer forms a heterointerface with the channel layer. The heterointerface is a tunnel channel for carries.
摘要翻译：根据一个实施例，一种半导体器件包括：衬底; 形成在所述衬底上的栅电极; 形成在栅电极下方的栅极绝缘膜; 通过使用沟道层材料形成在所述栅极绝缘膜下方的沟道层; 源极区域和漏极区域，形成在所述基板中，以在沟道方向上插入所述沟道层; 以及源极延伸层，其形成在沟道层和源极区域之间的衬底中，以与沟道层的源极侧端部重叠。源延伸层与沟道层形成异质界面。异步接口是一个用于载波的隧道通道。

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