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1. 发明授权

US09704870B2 Compact semiconductor memory device having reduced number of contacts, methods of operating and methods of making 有权
公开(公告)号：US09704870B2
公开(公告)日：2017-07-11
申请号：US15428921
申请日：2017-02-09
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C16/04 , H01L27/108 , G11C11/4096
CPC分类号： H01L27/10802 , G11C7/22 , G11C11/04 , G11C11/39 , G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C14/0018 , G11C2211/4016 , H01L23/528 , H01L29/1095 , H01L29/66825 , H01L29/66833 , H01L29/772 , H01L29/7841 , H01L29/7881
摘要： An integrated circuit including a link or string of semiconductor memory cells, wherein each memory cell includes a floating body region for storing data. The link or siring includes at least one contact configured to electrically connect the memory cells to at least one control line, and the number of contacts in the string or link is the same as or less than the number of memory cells in the string or link.

2. 发明申请

US20170018598A1 Memory Devices and Memory Device Forming Methods 审中-公开
标题翻译：存储器件和存储器件形成方法
公开(公告)号：US20170018598A1
公开(公告)日：2017-01-19
申请号：US15277551
申请日：2016-09-27
申请人： Micron Technology, Inc.
发明人： Chandra Mouli
IPC分类号： H01L27/24 , H01L29/66 , G11C13/00 , H01L45/00
CPC分类号： H01L27/2418 , G11C5/02 , G11C11/34 , G11C11/39 , G11C11/4026 , G11C11/5664 , G11C11/5678 , G11C11/5685 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/0014 , G11C13/0016 , G11C13/003 , G11C2013/009 , G11C2213/72 , G11C2213/74 , G11C2213/76 , G11C2216/08 , H01L29/6609 , H01L45/00 , H01L45/141 , H01L45/145 , H01L45/16
摘要： Some embodiments include memory devices having a wordline, a bitline, a memory element selectively configurable in one of three or more different resistive states, and a diode configured to allow a current to flow from the wordline through the memory element to the bitline responsive to a voltage being applied across the wordline and the bitline and to decrease the current if the voltage is increased or decreased. Some embodiments include memory devices having a wordline, a bitline, memory element selectively configurable in one of two or more different resistive states, a first diode configured to inhibit a first current from flowing from the bitline to the wordline responsive to a first voltage, and a second diode comprising a dielectric material and configured to allow a second current to flow from the wordline to the bitline responsive to a second voltage.
摘要翻译：一些实施例包括具有字线，位线，可选择性地以三种或更多种不同电阻状态中的一种状态配置的存储器元件的存储器件，以及被配置为允许电流从字线通过存储器元件流过到位线的二极管，电压施加在字线和位线之间，并且如果电压增加或减小则降低电流。一些实施例包括具有字线，位线，可选择性地以两种或多种不同电阻状态之一配置的存储器元件的存储器件，被配置为阻止第一电流响应于第一电压从位线流向字线的第一二极管，以及第二二极管，包括电介质材料，并被配置为响应于第二电压允许第二电流从字线流到位线。

3. 发明申请

US20160379984A1 Thyristor Memory Cell with Gate in Trench Adjacent the Thyristor 审中-公开
标题翻译：晶闸管记忆单元与闸流管相邻的晶闸管
公开(公告)号：US20160379984A1
公开(公告)日：2016-12-29
申请号：US15197640
申请日：2016-06-29
申请人： Kilopass Technology, Inc.
发明人： Harry Luan , Bruce L. Bateman , Valery Axelrad , Charlie Cheng
IPC分类号： H01L27/102 , G11C11/406 , H01L29/06
CPC分类号： H01L27/1027 , G11C11/4026 , G11C11/40622 , G11C2211/4068 , H01L27/1023 , H01L29/0649 , H01L29/749
摘要： A volatile memory array using vertical thyristors with gates, NMOS or PMOS, in trenches adjacent the thyristors is disclosed together with methods of fabricating the array.
摘要翻译：在与晶闸管相邻的沟槽中使用具有栅极，NMOS或PMOS的垂直晶闸管的易失性存储器阵列与制造阵列的方法一起公开。

4. 发明申请

US20160358924A1 SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR 有权
公开(公告)号：US20160358924A1
公开(公告)日：2016-12-08
申请号：US15238343
申请日：2016-08-16
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja , Zvi Or-Bach
IPC分类号： H01L27/108 , H01L29/10 , G11C11/4074 , H01L23/528 , H01L29/78
CPC分类号： H01L27/10802 , G11C7/22 , G11C11/04 , G11C11/39 , G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C14/0018 , G11C2211/4016 , H01L23/528 , H01L29/1095 , H01L29/66825 , H01L29/66833 , H01L29/772 , H01L29/7841 , H01L29/7881
摘要： An IC may include an array of memory cells formed in a semiconductor, including memory cells arranged in rows and columns, each memory cell may include a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; a buried region located within the memory cell and located adjacent to the floating body region, wherein the buried region has a second conductivity type, wherein the floating body region is bounded on a first side by a first insulating region having a first thickness and on a second side by a second insulating region having a second thickness, and a gate region above the floating body region and the second insulating region and is insulated from the floating body region by an insulating layer; and control circuitry configured to provide electrical signals to said buried region.

5. 发明授权

US09208840B2 Semiconductor memory device having an electrically floating body transistor 有权
标题翻译：具有电浮体晶体管的半导体存储器件
公开(公告)号：US09208840B2
公开(公告)日：2015-12-08
申请号：US14330083
申请日：2014-07-14
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja , Zvi Or-Bach
IPC分类号： G11C7/22 , G11C11/404 , H01L27/108 , H01L29/78 , H01L29/772 , G11C11/04
CPC分类号： H01L27/10802 , G11C7/22 , G11C11/04 , G11C11/39 , G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C14/0018 , G11C2211/4016 , H01L23/528 , H01L29/1095 , H01L29/66825 , H01L29/66833 , H01L29/772 , H01L29/7841 , H01L29/7881
摘要： A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.
摘要翻译：一种用于对具有行和列的存储器单元的半导体存储器阵列进行保持操作的方法，包括：将电信号施加到存储器单元的掩埋区域，其中每个存储器单元包括限定至少一部分的浮体区域所述浮体区域具有第一导电类型; 并且其中每个存储单元的所述埋入区位于所述存储单元内并且位于所述浮体区附近，所述掩埋区具有第二导电类型。

6. 发明授权

US08982633B2 Techniques for providing a direct injection semiconductor memory device 有权
标题翻译：提供直接注入半导体存储器件的技术
公开(公告)号：US08982633B2
公开(公告)日：2015-03-17
申请号：US13954660
申请日：2013-07-30
申请人： Micron Technology, Inc.
发明人： Srinivasa R. Banna , Michael A. Van Buskirk
IPC分类号： G11C16/04 , G11C7/00 , G11C11/402 , G11C11/403 , H01L27/102 , H01L27/108 , H01L29/78 , H01L27/082
CPC分类号： G11C7/00 , G11C11/4026 , G11C11/403 , G11C2211/4016 , H01L27/082 , H01L27/1023 , H01L27/108 , H01L27/10802 , H01L29/7841
摘要： Techniques for providing a direct injection semiconductor memory device are disclosed. In one particular exemplary embodiment, the techniques may be realized as a direct injection semiconductor memory device including a first region connected to a bit line extending in a first orientation and a second region connected to a source line extending in a second orientation. The direct injection semiconductor memory device may also include a body region spaced apart from and capacitively coupled to a word line extending in the second orientation, wherein the body region is electrically floating and disposed between the first region and the second region. The direct injection semiconductor memory device may further include a third region connected to a carrier injection line extending in the second orientation, wherein the first region, the second region, the body region, and the third region are disposed in sequential contiguous relationship.
摘要翻译：公开了提供直接注入半导体存储器件的技术。在一个特定示例性实施例中，技术可以被实现为直接注入半导体存储器件，其包括连接到沿第一取向延伸的位线的第一区域和连接到沿第二取向延伸的源极线的第二区域。直接注入半导体存储器件还可以包括与在第二取向上延伸的字线间隔开并且电容耦合到字线的主体区域，其中主体区域电浮置并且设置在第一区域和第二区域之间。直接注入半导体存储器件还可以包括连接到沿着第二取向延伸的载流子注入管线的第三区域，其中第一区域，第二区域，体区域和第三区域以顺序连续的关系设置。

7. 发明授权

US08654583B2 Memory cells, memory cell arrays, methods of using and methods of making 有权
标题翻译：存储单元，存储单元阵列，使用方法和制作方法
公开(公告)号：US08654583B2
公开(公告)日：2014-02-18
申请号：US13937612
申请日：2013-07-09
申请人： Yuniarto Widjaja
发明人： Yuniarto Widjaja
IPC分类号： G11C14/00
CPC分类号： G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0097 , G11C14/0018 , G11C14/0045 , G11C16/0416 , G11C2211/4016 , G11C2213/76 , G11C2213/79 , H01L27/1023 , H01L27/1052 , H01L27/10802 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7881 , H01L45/06 , H01L45/144 , H01L45/145
摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.
摘要翻译：提供半导体存储单元和存储单元阵列在至少一个实施例中，存储单元包括具有顶表面的衬底，该衬底具有选自p型导电类型和n型导电类型的第一导电类型 ; 具有选自p型和n型导电类型的第二导电类型的第一区域，所述第二导电类型不同于所述第一导电类型，所述第一区域形成在所述基板中并暴露在所述顶表面处; 具有第二导电类型的第二区域，第二区域形成在基板中，与第一区域间隔开并暴露在顶表面处; 位于第一和第二区域下方的衬底中的与第一和第二区域间隔开并且具有第二导电类型的掩埋层; 形成在所述第一和第二区域与所述掩埋层之间的体区，所述体区具有第一导电类型; 位于第一和第二区域之间并位于顶部表面之上的门; 以及非易失性存储器，被配置为在从身体区域传送时存储数据。

8. 发明申请

US20120081976A1 SEMICONDUCTOR MEMORY DEVICE HAVING AN ELECTRICALLY FLOATING BODY TRANSISTOR 失效
标题翻译：具有电浮标体晶体管的半导体存储器件
公开(公告)号：US20120081976A1
公开(公告)日：2012-04-05
申请号：US12897516
申请日：2010-10-04
申请人： Yuniarto Widjaja , Zvi Or-Bach
发明人： Yuniarto Widjaja , Zvi Or-Bach
IPC分类号： G11C7/00
CPC分类号： H01L27/10802 , G11C7/22 , G11C11/04 , G11C11/39 , G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/4094 , G11C11/4096 , G11C14/0018 , G11C2211/4016 , H01L23/528 , H01L29/1095 , H01L29/66825 , H01L29/66833 , H01L29/772 , H01L29/7841 , H01L29/7881
摘要： A method for performing a holding operation to a semiconductor memory array having rows and columns of memory cells, includes: applying an electrical signal to buried regions of the memory cells, wherein each of the memory cells comprises a floating body region defining at least a portion of a surface of the memory cell, the floating body region having a first conductivity type; and wherein the buried region of each memory cell is located within the memory cell and located adjacent to the floating body region, the buried region having a second conductivity type.
摘要翻译：一种用于对具有行和列的存储器单元的半导体存储器阵列进行保持操作的方法，包括：将电信号施加到存储器单元的掩埋区域，其中每个存储器单元包括限定至少一部分的浮体区域所述浮体区域具有第一导电类型; 并且其中每个存储单元的所述埋入区位于所述存储单元内并且位于所述浮体区附近，所述掩埋区具有第二导电类型。

9. 发明授权

US07893478B2 Semiconductor storage device and driving method thereof 失效
标题翻译：半导体存储装置及其驱动方法
公开(公告)号：US07893478B2
公开(公告)日：2011-02-22
申请号：US12060522
申请日：2008-04-01
申请人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
发明人： Tomoki Higashi , Takashi Ohsawa , Ryo Fukuda
IPC分类号： H01L27/108 , H01L29/94 , H01L23/52 , H01L21/70 , H01L29/66
CPC分类号： H01L27/1022 , G11C11/4023 , G11C11/4026 , G11C11/405 , G11C11/4085 , G11C2211/4016 , H01L21/8249 , H01L21/84 , H01L27/0207 , H01L27/105 , H01L27/1052 , H01L27/108 , H01L27/10802 , H01L27/1203 , H01L29/7841
摘要： This disclosure concerns a semiconductor storage device comprising a semiconductor layer provided on the insulation layer provided on the semiconductor substrate; a source layer and a drain layer provided in the semiconductor layer; a body provided between the source layer and the drain layer, the body being in an electrically floating state; an emitter layer contacting with the source layer, the emitter layer having an opposite conductive type to the source layer; a word line including the source layer, the drain layer, and the body, the word line being provided to memory cells arrayed in a first direction in a plurality of tow-dimensionally arranged memory cells; a source line connected to the source layers of the memory cells arrayed in the first direction; and a bit line connected to the drain layers of the memory cells arrayed in a second direction intersecting the first direction.
摘要翻译：本公开涉及一种半导体存储装置，其包括设置在设置在半导体衬底上的绝缘层上的半导体层; 设置在所述半导体层中的源极层和漏极层; 设置在所述源极层和所述漏极层之间的主体，所述主体处于电浮动状态; 与源极层接触的发射极层，发射极层与源极层具有相反的导电类型; 包括源层，漏极层和主体的字线，字线被提供给在多个维度上排列的存储单元中沿第一方向排列的存储单元; 连接到沿着第一方向排列的存储单元的源层的源极线; 以及连接到沿与第一方向相交的第二方向排列的存储单元的漏极层的位线。

10. 发明授权

US09978450B2 Memory cells, memory cell arrays, methods of using and methods of making 有权
公开(公告)号：US09978450B2
公开(公告)日：2018-05-22
申请号：US15810400
申请日：2017-11-13
申请人： Zeno Semiconductor, Inc.
发明人： Yuniarto Widjaja
IPC分类号： G11C11/00 , G11C14/00 , G11C13/00 , H01L45/00 , G11C11/56 , G11C11/4074 , G11C11/402 , H01L27/108 , H01L27/102 , H01L27/105 , H01L29/788 , H01L29/78 , H01L29/66 , H01L27/24 , G11C11/404 , G11C16/04
CPC分类号： G11C11/4026 , G11C11/404 , G11C11/4074 , G11C11/56 , G11C13/0002 , G11C13/0004 , G11C13/0007 , G11C13/003 , G11C13/0038 , G11C13/0097 , G11C14/0018 , G11C14/0045 , G11C16/0416 , G11C2211/4016 , G11C2213/76 , G11C2213/79 , H01L27/1023 , H01L27/1052 , H01L27/10802 , H01L27/24 , H01L29/66825 , H01L29/66833 , H01L29/7841 , H01L29/7881 , H01L45/06 , H01L45/144 , H01L45/145
摘要： A semiconductor memory cell and arrays of memory cells are provided In at least one embodiment, a memory cell includes a substrate having a top surface, the substrate having a first conductivity type selected from a p-type conductivity type and an n-type conductivity type; a first region having a second conductivity type selected from the p-type and n-type conductivity types, the second conductivity type being different from the first conductivity type, the first region being formed in the substrate and exposed at the top surface; a second region having the second conductivity type, the second region being formed in the substrate, spaced apart from the first region and exposed at the top surface; a buried layer in the substrate below the first and second regions, spaced apart from the first and second regions and having the second conductivity type; a body region formed between the first and second regions and the buried layer, the body region having the first conductivity type; a gate positioned between the first and second regions and above the top surface; and a nonvolatile memory configured to store data upon transfer from the body region.

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