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41. 发明授权

US06909628B2 High density magnetic RAM and array architecture using a one transistor, one diode, and one MTJ cell 有权
标题翻译：使用一个晶体管，一个二极管和一个MTJ单元的高密度磁性RAM和阵列架构
公开(公告)号：US06909628B2
公开(公告)日：2005-06-21
申请号：US10366498
申请日：2003-02-13
申请人： Wen-Chin Lin , Denny D. Tang , Yu Der Chih
发明人： Wen-Chin Lin , Denny D. Tang , Yu Der Chih
IPC分类号： G11C11/00 , G11C11/15 , G11C11/16 , H01L43/00 , H03K5/02
CPC分类号： G11C11/16
摘要： A new magnetic RAM cell device is achieved. The device comprises a MTJ cell comprising a free layer and a pinned layer separated by a dielectric layer. A diode is coupled between the free layer and a reading line. A writing switch is coupled between a first end of the pinned layer and a first writing line. A second end of the pinned layer is coupled to a second writing line. Architectures using MRAM cells are disclosed.
摘要翻译：实现了新的磁性RAM单元装置。该器件包括MTJ电池，其包括由电介质层分离的自由层和钉扎层。二极管耦合在自由层和读取线之间。写入开关耦合在固定层的第一端和第一写入线之间。固定层的第二端耦合到第二写入线。公开了使用MRAM单元的架构。

42. 发明申请

US20050104656A1 Amplifier 有权
标题翻译：放大器
公开(公告)号：US20050104656A1
公开(公告)日：2005-05-19
申请号：US10929524
申请日：2004-08-31
申请人： Haruo Kojima
发明人： Haruo Kojima
IPC分类号： H03K5/02 , H03F1/32 , H03F3/21 , H03F3/72 , H03G3/20
CPC分类号： H03F3/72 , H03F2200/405 , H03F2203/7227
摘要： An amplifier includes a plurality of power amplifier elements connected in cascaded multiple stages, a first bias power supply, a second bias power supply, a switching circuit configured to switch a first output supplied from the first bias power supply in response to a modulation pulse so as to transmit the first output to the plurality of power amplifier elements, a pulse differentiating circuit configured to differentiate the modulation pulse by a given time constant, and an adder circuit configured to add the differentiated modulation pulse and a second output of the second bias power supply so as to transmit the differentiated modulation pulse added to the second output as an input bias voltage to at least one of the plurality of power amplifier elements except for a final stage in the cascaded multiple stages.
摘要翻译：放大器包括以级联多级连接的多个功率放大器元件，第一偏置电源，第二偏置电源，被配置为响应于调制脉冲来切换从第一偏置电源提供的第一输出的开关电路，为了将第一输出发送到多个功率放大器元件，配置为将调制脉冲区分给定时间常数的脉冲差分电路和被配置为将差分调制脉冲和第二偏置功率的第二输出相加的加法器电路供给，以将除了作为级联多级的最后级之外的多个功率放大器元件中的至少一个发送作为输入偏置电压的添加到第二输出的微分调制脉冲。

43. 发明授权

US06861889B2 Amplitude converting circuit 失效
标题翻译：幅度转换电路
公开(公告)号：US06861889B2
公开(公告)日：2005-03-01
申请号：US10450268
申请日：2002-02-26
申请人： Youichi Tobita
发明人： Youichi Tobita
IPC分类号： G09G3/20 , G09G3/36 , H03K3/356 , H03K5/02 , H03K17/06 , H03K19/00 , H03L5/00
CPC分类号： H03K3/356113 , G09G2310/0289 , H03K17/063
摘要： A level shifter includes first and second P type thin film transistors (TFTs) and first and second N type TFTs for latching levels of first and second output nodes, third and fourth N type TFTs for setting levels of the first and second output nodes, and first and second resistance elements and first and second capacitors for applying, between the gate-source of the third and fourth N type TFTs, a voltage higher than a voltage of an input signal, in response to rising and falling edges of the input signal respectively.
摘要翻译：电平移位器包括第一和第二P型薄膜晶体管（TFT）以及用于锁存第一和第二输出节点电平的第一和第二N型TFT，用于设置第一和第二输出节点电平的第三和第四N型TFT，以及第一和第二电阻元件以及第一和第二电容器，用于响应于输入信号的上升沿和下降沿，在第三和第四N型TFT的栅极源之间施加比输入信号的电压高的电压。

44. 发明授权

US6154069A Circuit for driving capacitive load 失效
标题翻译：用于驱动电容性负载的电路
公开(公告)号：US6154069A
公开(公告)日：2000-11-28
申请号：US978818
申请日：1997-11-26
申请人： Heihachiro Ebihara
发明人： Heihachiro Ebihara
IPC分类号： G09G3/36 , H03F3/30 , H03K5/02 , H03K19/013 , H03K19/018 , H03B1/00
CPC分类号： G09G3/3696 , H03F3/3066 , H03K19/013 , H03K19/0136 , H03K19/01825 , H03K5/02 , G09G2320/0209
摘要： A circuit for driving a capacitive load using a booster having a low power consumption, which amplifies spike-like signals at high speeds and produces a large voltage and a large current, and wherein two transistors 104 and 111 are connected in series across a first power source H1 and a second power source L1 having a potential lower than that of the first power source. An output terminal OUT is provided at a portion where the two transistors are connected together, and the first transistor 104 connected between the first power source and the output terminal has a complementary relationship to the second transistor 11 connected between the output terminal and the second power source. The first transistor 104 is constituted by a PNP-type bipolar transistor or a P-type field-effect transistor, the second transistor 111 is constituted by an NPN-type transistor or an N-type field-effect transistor, and between an input terminal IN and a control terminal of each of the transistors are connected in parallel a capacitor and a means that applies a bias to the control terminal.
摘要翻译：一种用于使用具有低功耗的升压器来驱动电容性负载的电路，其以高速放大尖峰状信号并产生大电压和大电流，并且其中两个晶体管104和111串联连接跨第一功率源H1和具有低于第一电源的电位的第二电源L1。输出端子OUT设置在两个晶体管连接在一起的部分，并且连接在第一电源和输出端子之间的第一晶体管104与连接在输出端子和第二电源之间的第二晶体管11互补资源。第一晶体管104由PNP型双极晶体管或P型场效应晶体管构成，第二晶体管111由NPN型晶体管或N型场效应晶体管构成，在输入端 IN和每个晶体管的控制端并联连接电容器和向控制端施加偏压的装置。

45. 发明授权

US6133767A Digital driver circuit for an integrated circuit 失效
标题翻译：用于集成电路的数字驱动电路
公开(公告)号：US6133767A
公开(公告)日：2000-10-17
申请号：US558670
申请日：1995-11-16
申请人： Knut Caesar , Norbert Greitschus
发明人： Knut Caesar , Norbert Greitschus
IPC分类号： H03M1/12 , H03K5/02 , H03K17/16 , H03K17/687 , H03K19/003 , H03K19/0185 , H03K3/00
CPC分类号： H03K19/00384 , H03K19/018585 , H03K5/02
摘要： An integrated driver circuit for driving different capacitive loads, which includes a setting element. The setting element develops a setting signal S for a given numerical measure signal M. The numerical measure signal M is developed by an input device, which is coupled to the setting element. The numerical measure signal M corresponds to one of the different capacitive loads which is driven by the driver circuit. Coupled to the setting element is an output stage, which provides an output current that corresponds to the setting signal S.
摘要翻译：一种用于驱动不同容性负载的集成驱动电路，其包括设定元件。设定元件对于给定的数字测量信号M产生设定信号S.数字测量信号M由耦合到设定元件的输入设备展开。数字测量信号M对应于由驱动器电路驱动的不同容性负载之一。耦合到设置元件是输出级，其提供对应于设置信号S的输出电流。

46. 发明授权

US6084459A Voltage level shifting circuit 失效
标题翻译：电压电平移位电路
公开(公告)号：US6084459A
公开(公告)日：2000-07-04
申请号：US953510
申请日：1997-10-17
申请人： Jae-Hong Jeong
发明人： Jae-Hong Jeong
IPC分类号： H03K19/0185 , H03K3/356 , H03K5/02 , H03L5/00
CPC分类号： H03K3/356104
摘要： An improved voltage level shifting circuit which is capable of increasing a level shifting speed and reducing a current consumption and layout area by decreasing a pull-up capacity of the pull-up PMOS transistors in a side in which a voltage level is shifted to a low level and increasing a pull-up capacity through the NMOS transistors in a side in which a voltage level is shifted to a high level. The voltage level shifting circuit includes a pull-up PMOS transistor and a pull-down NMOS transistor connected in series between a voltage Vpp terminal and a voltage Vss terminal and having a common drain which acts a first voltage terminal, a pull-up PMOS transistor and a pull-down NMOS transistor connected in series between the voltage Vpp terminal and the voltage Vss terminal, configured symmetrically with respect to the pull-up PMOS transistor and pull-down NMOS transistor, and having a common drain which acts as a second voltage terminal, a first conductive type MOS transistor a source of which is connected with a gate of the pull-up PMOS transistor and the second voltage terminal, respectively and a gate of which is connected with an input terminal, and a second conductive type MOS transistor a source of which is connected with a gate of the pull-up PMOS transistor and the first voltage terminal, respectively, and a gate of which is connected with the input terminal through an inverter.
摘要翻译：一种改进的电压电平移位电路，其能够通过减小上拉PMOS晶体管在电压电平变为低电平的一侧的上拉电容而提高电平移位速度并降低电流消耗和布局面积并且通过在其中电压电平转移到高电平的一侧中的NMOS晶体管增加上拉电容。电压电平移位电路包括串联连接在电压Vpp端子和电压Vss端子之间的上拉PMOS晶体管和下拉式NMOS晶体管，并具有作为第一电压端子的共用漏极，上拉PMOS晶体管以及串联连接在电压Vpp端子和电压Vss端子之间的下拉式NMOS晶体管，其相对于上拉PMOS晶体管和下拉式NMOS晶体管对称配置，并具有用作第二电压的公共漏极端子，第一导电型MOS晶体管，其源极分别与上拉PMOS晶体管的栅极和第二电压端子连接，其栅极与输入端子连接，第二导电型MOS晶体管其源极分别与上拉PMOS晶体管和第一电压端子的栅极连接，并且其栅极通过i连接到输入端子 nverter

47. 发明授权

US5914867A Voltage generator-booster for supplying a pulsating voltage having approximately constant voltage levels 失效
标题翻译：用于提供具有近似恒定电压电平的脉动电压的电压发生器 - 升压器
公开(公告)号：US5914867A
公开(公告)日：1999-06-22
申请号：US631574
申请日：1996-04-12
申请人： Luigi Pascucci
发明人： Luigi Pascucci
IPC分类号： H03K5/02 , G05F3/24 , G11C11/34 , H02M3/07 , H03K19/096 , H02M7/25
CPC分类号： H02M3/07 , G05F3/242
摘要： A generator-booster includes a bootstrap capacitor coupled between an output node and a pull-up node. A bootstrap control stage is coupled to the pull-up node and receives a pump signal with two states determining a precharge step and a pull-up step of the bootstrap capacitor. A precharge limiting transistor is supplied with a precharge reference signal and is coupled to the output node and the bootstrap capacitor to prevent a bootstrap capacitor from being charged in excess of a value determined by the precharge reference signal. A limiting stage is coupled to the output node and the bootstrap capacitor to prevent a voltage of the output node from exceeding a value determined by the limiting stage. The bootstrap control stage also provides for decoupling the pull-up node from the pump signal during the pull-up step, after the limiting stage has been turned on.
摘要翻译：发生器 - 升压器包括耦合在输出节点和上拉节点之间的自举电容器。引导控制级耦合到上拉节点并且接收具有确定自举电容器的预充电步骤和上拉步骤的两种状态的泵浦信号。预充电限制晶体管被提供有预充电参考信号，并且耦合到输出节点和自举电容器，以防止自举电容器被充电超过由预充电参考信号确定的值。限制级耦合到输出节点和自举电容器，以防止输出节点的电压超过由限制级确定的值。引导控制级还提供在上拉步骤中，在限制级已经接通之后，将上拉节点与泵浦信号去耦。

48. 发明授权

US5854567A Low loss integrated circuit with reduced clock swing 失效
标题翻译：低损耗集成电路，减少时钟摆幅
公开(公告)号：US5854567A
公开(公告)日：1998-12-29
申请号：US716440
申请日：1996-09-24
申请人： Stefan Meier , Erik De Man
发明人： Stefan Meier , Erik De Man
IPC分类号： G06F1/32 , G06F1/04 , H02M3/07 , H03K5/02 , H03K19/00 , H03K17/687 , G05F1/10 , H03K19/094 , H03K19/096
CPC分类号： H03K19/0016
摘要： The integrated circuit with a clock system, particularly a CMOS circuit with extensive pipelining, whereby an optimally low overall dissipated power is effected in that a clock driver circuit is provided with a specifically wired driver output stage that generates a clock supply voltage that corresponds to about half the value of a general supply voltage. A great reduction of the dissipated power can be achieved given relative slight sacrifices in the performance capability.
摘要翻译： PCT No.PCT / DE95 / 00335 Sec。 371日期：1996年9月24日 102（e）1996年9月24日PCT 1995年3月10日PCT公布。公开号WO95 / 26077 日期1995年9月28日具有时钟系统的集成电路，特别是具有广泛流水线的CMOS电路，由此实现了最佳的低总体耗散功率，因为时钟驱动器电路具有产生时钟电源的专用线驱动器输出级电压对应于一般电源电压值的大约一半。在性能方面给予相对轻微的牺牲，可以大大减少耗散功率。

49. 发明授权

US5751186A Operational amplifier circuit with an extended input voltage range 失效
标题翻译：具有扩展输入电压范围的运算放大器电路
公开(公告)号：US5751186A
公开(公告)日：1998-05-12
申请号：US659585
申请日：1996-06-06
申请人： Tomoaki Nakao
发明人： Tomoaki Nakao
IPC分类号： H03K5/02 , H03F3/30 , H03F3/45 , H03F3/72 , H03K19/0948 , H03K17/687
CPC分类号： H03F3/3055 , H03F3/4521 , H03F3/72
摘要： An operational amplifier circuit 21 comprises transistors N14, N15 in a first output amplifier circuit 24, and transistors P24, P25 in a second output amplifier circuit 25. When a second differential amplifier circuit 23 is cut off, the output is driven by transistor P13 and transistors N14, N15. When a first differential amplifier circuit 22 is cut off, the output is driven by transistor N23 and transistors P24, P25. Therefore, if such a voltage as to cut off one differential amplifier circuit is given from opposite phase and in-phase input terminals 31, 32, the output can be produced. In such constitution, without using depletion type transistors that require particular manufacturing process, the range of the voltage that can be entered in the input terminal can be extended.
摘要翻译：运算放大器电路21包括第一输出放大器电路24中的晶体管N14，N15，以及第二输出放大器电路25中的晶体管P24，P25。当第二差分放大器电路23截止时，输出由晶体管P13驱动，晶体管N14，N15。当第一差分放大器电路22截止时，输出由晶体管N23和晶体管P24，P25驱动。因此，如果从相位相位和同相输入端子31,32给出截止一个差分放大器电路的这种电压，则可以产生输出。在这种结构中，不需要使用需要特定制造工艺的耗尽型晶体管，可以扩展可以输入到输入端子中的电压的范围。

50. 发明授权

US5742198A Waveform shaping apparatus 失效
标题翻译：波形整形装置
公开(公告)号：US5742198A
公开(公告)日：1998-04-21
申请号：US687915
申请日：1996-07-29
申请人： Masakiyo Horie , Takuya Harada
发明人： Masakiyo Horie , Takuya Harada
IPC分类号： G01P3/489 , G01D5/244 , G01R19/165 , H03K5/02 , H03K5/08 , H03K5/1252 , H03B1/00
CPC分类号： G01D5/24476 , H03K5/02 , H03K5/088
摘要： An input voltage Va and a threshold voltage Vc are compared in a comparator 21 to shaping the waveform of a sensor signal. The period of the output signal of comparator 21 is measured by a period measuring circuit 4. A stepped waveform voltage generating circuit 5 generates a stepped waveform voltage based on the measured period. The stepped waveform voltage is converted into corresponding current in a V-I conversion circuit 6. The current of V-I conversion circuit 6 is supplied to a resistance 23d or 23e via an analog switch 22a or 22b which turns on or off in response to the operation of comparator 21, thereby applying a stepped offset voltage to input voltage Va threshold voltage Vc to perform the hysteresis operation.
摘要翻译：在比较器21中比较输入电压Va和阈值电压Vc，以对传感器信号的波形进行整形。比较器21的输出信号的周期由周期测量电路4测量。阶梯波形电压产生电路5基于测量周期产生阶梯波形电压。在VI转换电路6中将阶梯波形电压转换成相应的电流.VVI转换电路6的电流经由模拟开关22a或22b被提供给电阻23d或22b，模拟开关22a或22b响应于比较器的操作而导通或截止从而对输入电压Va阈值电压Vc施加阶梯式偏移电压以执行滞后操作。

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