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41. 发明授权

US09741397B2 Semiconductor memory device 有权
公开(公告)号：US09741397B2
公开(公告)日：2017-08-22
申请号：US14632413
申请日：2015-02-26
申请人： Rohm Co., Ltd.
发明人： Kazuhisa Ukai
IPC分类号： G11C11/24 , G11C5/02 , G11C11/412 , G11C29/12 , H01L27/02 , H01L27/105 , H01L27/108 , H01L27/11 , G11C7/06 , G11C7/14 , G11C11/4099
CPC分类号： G11C5/025 , G11C7/06 , G11C7/14 , G11C11/4099 , G11C11/412 , G11C29/1201 , H01L27/0207 , H01L27/105 , H01L27/10894 , H01L27/10897 , H01L27/1104 , H01L27/1116
摘要： A semiconductor memory device includes a memory array including a plurality of element blocks, the plurality of element blocks including end-portion element blocks arranged at an end portion of the memory array, and at least one dummy block disposed adjacent to the end-portion element blocks, the at least one dummy block being not in practical use. A layout pattern of the at least one dummy block is configured to correspond to only a portion of a layout pattern of the plurality of element blocks.

42. 发明授权

US09685226B2 Tracking signals in memory write or read operation 有权
公开(公告)号：US09685226B2
公开(公告)日：2017-06-20
申请号：US14822391
申请日：2015-08-10
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING COMPANY, LTD.
发明人： Chih-Chieh Chiu , Hong-Chen Cheng
IPC分类号： G11C7/00 , G11C11/419 , G11C7/22 , G11C7/08 , G11C11/4076 , G11C11/4099
CPC分类号： G11C11/419 , G11C7/08 , G11C7/227 , G11C11/4076 , G11C11/4099
摘要： A signal generating circuit includes a first circuit, a tracking circuit, and a delay circuit. The delay circuit is coupled with the first circuit and the tracking circuit. The first circuit is configured to receive a first clock signal and an output signal from an output of the delay circuit, and to generate a second clock signal and at least one first tracking signal. The tracking circuit is configured to receive the at least one first tracking signal and to generate a second tracking signal. The delay circuit is configured to receive the second clock signal and the second tracking signal and to generate the output signal.

43. 发明授权

US09672895B2 Sense amplifier, semiconductor memory device using thereof and read method thereof 有权
公开(公告)号：US09672895B2
公开(公告)日：2017-06-06
申请号：US15132258
申请日：2016-04-19
申请人： Artur Antonyan
发明人： Artur Antonyan
IPC分类号： G11C7/06 , G11C11/4091 , G11C11/4099 , G11C11/408
CPC分类号： G11C11/4091 , G11C11/4087 , G11C11/4099 , G11C2207/002
摘要： A sense amplifier is provided which includes a first load supplied with a selection cell current from a read bit line connected to a selected memory cell; a second load supplied with a reference current from a reference read bit line connected to a reference cell, a resistance value of the second load being different from a resistance value of the first load; and a sensing unit configured to correct a level of the reference current based on a resistance ratio of the first and second loads and to compare the selection cell current and the corrected reference current.

44. 发明申请

US20170154669A1 DATA RECEPTION CHIP 审中-公开
公开(公告)号：US20170154669A1
公开(公告)日：2017-06-01
申请号：US14969395
申请日：2015-12-15
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： Hongquan SUN
IPC分类号： G11C11/4099
CPC分类号： G11C11/4099 , G11C7/1084
摘要： A data reception chip coupled to an external memory comprising a first input-output pin to output first data and including a comparison module and a voltage generation module is provided. The comparison module is coupled to the first input-output pin to receive the first data and compares the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage and includes a plurality of first resistors and a first selection unit. The first resistors are connected in series with one another and dividing a first operation voltage to generate a plurality of first divided voltages. The first selection unit selects one of the first divided voltages as the first reference voltage according to a first control signal.

45. 发明授权

US09547571B2 Block behavior tracking in a memory system 有权
标题翻译：在内存系统中阻止行为跟踪
公开(公告)号：US09547571B2
公开(公告)日：2017-01-17
申请号：US14717608
申请日：2015-05-20
申请人： SanDisk Technologies Inc.
发明人： Niles Yang , Rohit Sehgal , Abhi Kashyap
IPC分类号： G06F11/10 , G06F11/263 , G06F3/06 , G11C16/34 , G11C29/50 , G11C7/14 , G11C8/14 , G11C11/4099
CPC分类号： G11C8/14 , G06F11/1072 , G11C7/14 , G11C11/4099 , G11C11/5628 , G11C11/5642 , G11C16/0483 , G11C16/08 , G11C16/26 , G11C16/3404 , G11C16/3427 , G11C16/349 , G11C16/3495 , G11C29/028 , G11C29/24 , G11C29/42 , G11C29/50004 , G11C2029/0409 , G11C2029/0411 , G11C2029/5004
摘要： A storage device with a memory may include memory block health monitoring and behavior tracking. Each memory block may be analyzed based on one or more dummy wordlines within the block may not be accessible for normal data storage. The dummy wordlines may be programmed with a known data pattern that can be tracked and analyzed for potential errors, which may be used as representation of the health of the memory block. Adjustments can be made to the operating parameters (e.g. read voltages) to optimize each memory block based on its error analysis.
摘要翻译：具有存储器的存储设备可以包括记忆体健康监测和行为跟踪。可以基于块内的一个或多个虚拟字线来分析每个存储器块，对于正常数据存储可能不可访问。虚拟字线可以用已知的数据模式进行编程，该数据模式可被跟踪和分析潜在的错误，这可能被用作表示存储块的健康状况。可以对操作参数（例如读取电压）进行调整，以根据其误差分析优化每个存储器块。

46. 发明授权

US09536594B1 Data reception chip 有权
标题翻译：数据接收芯片
公开(公告)号：US09536594B1
公开(公告)日：2017-01-03
申请号：US14969350
申请日：2015-12-15
申请人： VIA Alliance Semiconductor Co., Ltd.
发明人： Hongquan Sun
IPC分类号： G11C7/06 , G11C11/4099 , G11C11/4093
CPC分类号： G11C11/4099 , G11C7/1084 , G11C11/4093 , H03K5/082
摘要： A data reception chip coupled to an external memory including a first input-output pin to output first data and including a comparison module, a voltage generation module, a logic unit, a detection module and a switching module is provided. The comparison module is coupled to the first input-output pin to configure to receive the first data. The comparison module compares the first data with a first reference voltage to identify the value of the first data. The voltage generation module is configured to generate the first reference voltage. The logic unit is coupled to the comparison module and the voltage generation module and outputs at least one switching signal. The detection module detects the logic unit to generate at least one detection signal. The switching module transmits the detection signal to a test pin according to the switching signal.
摘要翻译：一种数据接收芯片，其耦合到包括第一输入 - 输出引脚的外部存储器，以输出第一数据，并且包括比较模块，电压产生模块，逻辑单元，检测模块和切换模块。比较模块耦合到第一输入 - 输出引脚以配置为接收第一数据。比较模块将第一数据与第一参考电压进行比较，以识别第一数据的值。电压产生模块被配置为产生第一参考电压。逻辑单元耦合到比较模块和电压产生模块，并输出至少一个开关信号。检测模块检测逻辑单元以产生至少一个检测信号。切换模块根据切换信号将检测信号发送到测试引脚。

47. 发明授权

US09443563B2 Semiconductor device and driving method thereof 有权
公开(公告)号：US09443563B2
公开(公告)日：2016-09-13
申请号：US14678098
申请日：2015-04-03
申请人： SEMICONDUCTOR ENERGY LABORATORY CO., LTD.
发明人： Tomoaki Atsumi , Yoshiya Takewaki
IPC分类号： G11C5/10 , G11C11/4091 , G11C11/406 , G11C11/401 , G11C11/404 , G11C11/4099 , H01L27/12 , H01L27/108
CPC分类号： G11C5/10 , G11C11/401 , G11C11/404 , G11C11/406 , G11C11/4091 , G11C11/4099 , H01L27/10873 , H01L27/10897 , H01L27/1218 , H01L27/1225
摘要： In a memory module including a memory cell array including memory cells arranged in matrix, each including a first transistor using an oxide semiconductor and a first capacitor; a reference cell including a p-channel third transistor, a second capacitor, and a second transistor using an oxide semiconductor; and a refresh timing detection circuit including a resistor and a comparator, wherein when a potential is supplied to the first capacitor through the first transistor, a potential is supplied to the second capacitor through the second transistor, wherein a drain current value of the third transistor is changed in accordance with the potential stored in the second capacitor, and wherein when the drain current value of the third transistor is higher than a given value, a refresh operation of the memory cell array and the reference cell are performed.

48. 发明授权

US09349432B2 Reference voltage modification in a memory device 有权
公开(公告)号：US09349432B2
公开(公告)日：2016-05-24
申请号：US14694067
申请日：2015-04-23
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Joab D. Henderson , Kyu-hyoun Kim , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G11C11/406 , G11C11/4099 , G11C11/4076 , G11C11/4091
CPC分类号： G11C11/406 , G11C11/4076 , G11C11/4091 , G11C11/4099
摘要： A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.

49. 发明授权

US09224450B2 Reference voltage modification in a memory device 有权
标题翻译：存储器件中的参考电压修改
公开(公告)号：US09224450B2
公开(公告)日：2015-12-29
申请号：US13889528
申请日：2013-05-08
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Joab D. Henderson , Kyu-hyoun Kim , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G11C7/00 , G11C11/406 , G11C11/4099
CPC分类号： G11C11/406 , G11C11/4076 , G11C11/4091 , G11C11/4099
摘要： A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.
摘要翻译：公开了一种用于修改存储器件中的刷新之间的参考电压的方法和装置。存储器阵列可以包括多个存储器单元。存储器件还可以包括读出放大器。读出放大器可以被配置为使用参考电压从多个存储单元读取数据。存储器件还可以包括读出放大器参考电压修改电路。感测放大器参考电压修改电路可以被配置为响应于检测到触发事件来检测触发事件并修改参考电压。

50. 发明授权

US09117696B2 Semiconductor devices having balancing capacitor and methods of forming the same 有权
标题翻译：具有平衡电容器的半导体器件及其形成方法
公开(公告)号：US09117696B2
公开(公告)日：2015-08-25
申请号：US14077834
申请日：2013-11-12
申请人： Samsung Electronics Co., Ltd.
发明人： Jong-Un Kim , Yoo-Sang Hwang , Hyun-Woo Chung
IPC分类号： H01L21/02 , H01L27/108 , G11C11/4097 , G11C11/4099
CPC分类号： H01L27/10897 , G11C11/4097 , G11C11/4099 , H01L27/10814 , H01L27/10885 , H01L27/10894
摘要： A semiconductor memory device includes a substrate including cell block, a balancing block, and a sense block. A plurality of cell bit lines are formed in the cell block of. A plurality of cell plugs are formed adjacent to side surfaces of the bit lines. Cell inner spacers, air spacers, and cell outer spacers are formed between the cell bit lines and the cell plugs. A plurality of balancing bit lines are formed in the balancing block. A plurality of balancing plugs are formed adjacent to side surfaces of the balancing bit lines. Balancing inner spacers and balancing outer spacers are formed between the balancing bit lines and the balancing plugs. The balancing bit lines and at least some of the cell bit lines are connected to the sense block.
摘要翻译：半导体存储器件包括包括单元块，平衡块和感测块的衬底。在单元块中形成多个单元位线。在位线的侧面附近形成多个电池插头。在单元位线和电池插头之间形成电池内隔板，空气间隔件和电池外隔板。在平衡块中形成多个平衡位线。在平衡位线的侧表面附近形成多个平衡塞。在平衡位线和平衡插头之间形成平衡内部间隔件和平衡外部间隔件。平衡位线和至少一些单元位线连接到感测块。

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