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1. 发明授权

US11200112B1 Method and apparatus to reduce bandwidth overhead of CRC protection on a memory channel 有权
公开(公告)号：US11200112B1
公开(公告)日：2021-12-14
申请号：US17000974
申请日：2020-08-24
申请人： International Business Machines Corporation
发明人： Kevin M. Mcilvain , Warren E. Maule , Stephen Glancy , Kyu-hyoun Kim , Edgar R. Cordero
IPC分类号： G06F11/10 , G06F13/28 , G06F11/30 , G06F11/16
摘要： A method and/or system for checking the bus/interface between a host and a memory system during memory access operations includes a memory system having one or more of the data memory devices and a spare memory device; providing a bus/interface between a host and the memory system; selecting information on a per memory device basis to associate with a spare memory device; disassociating the selected information from the one or more data memory devices and associating the selected information with the spare memory device; adding Cyclical Redundancy Check (CRC) code to the one or more data memory devices from which the selected information was disassociated; transferring the CRC code and information over the bus and interface between the host and the memory system; and checking the bus interface with the CRC code added to the one or more data memory devices.

2. 发明授权

US09792209B2 Method and apparatus for cache memory data processing 有权
公开(公告)号：US09792209B2
公开(公告)日：2017-10-17
申请号：US14573970
申请日：2014-12-17
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , David M. Daly , Robert K. Montoye , Saravanan Sethuraman , Diyanesh B. Chinnakkonda Vidyapoornachary
IPC分类号： G06F13/40 , G06F12/08 , G06F12/0811 , G06F13/16 , G06F9/455 , G06F9/50 , G06F12/0831 , G06F12/00 , G06F3/00
CPC分类号： G06F12/0811 , G06F3/00 , G06F9/45558 , G06F9/50 , G06F12/0833 , G06F13/1673 , G06F13/4045 , G06F2009/45583 , G06F2212/1016 , G06F2212/283 , G06F2212/62
摘要： Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.

3. 发明授权

US09471540B2 Detecting TSV defects in 3D packaging 有权
标题翻译：检测3D封装中的TSV缺陷
公开(公告)号：US09471540B2
公开(公告)日：2016-10-18
申请号：US13733198
申请日：2013-01-03
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Anand Haridass , Girisankar Paulraj , Diyanesh B. Vidyapoornachary
IPC分类号： G01R31/26 , G06F17/00 , H01L21/66 , G01R31/3185 , H01L25/065
CPC分类号： G06F17/00 , G01R31/2607 , G01R31/318513 , H01L22/34 , H01L25/0657 , H01L2225/06541 , H01L2924/0002 , H01L2924/00
摘要： A computer determines a threshold signal voltage of a semiconductor device. The computer determines a first expected signal propagation time for a signal travelling through a first test path of the semiconductor device. The computer transmits a first signal through the first test path. The computer measures a signal voltage and signal propagation time of the first signal. The computer determines that the signal voltage of the first signal does not reach or exceed the threshold signal voltage within the first expected signal propagation time. The computer determines that the first test path contains a defect.
摘要翻译：计算机确定半导体器件的阈值信号电压。计算机确定通过半导体器件的第一测试路径行进的信号的第一预期信号传播时间。计算机通过第一测试路径发送第一信号。计算机测量第一信号的信号电压和信号传播时间。计算机确定第一信号的信号电压在第一预期信号传播时间内未达到或超过阈值信号电压。计算机确定第一个测试路径包含缺陷。

4. 发明授权

US09418722B2 Prioritizing refreshes in a memory device 有权
公开(公告)号：US09418722B2
公开(公告)日：2016-08-16
申请号：US14878174
申请日：2015-10-08
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Joab D. Henderson , Kyu-hyoun Kim , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G11C11/406 , G11C7/24 , G11C11/4076 , G11C11/403
CPC分类号： G11C11/406 , G11C7/24 , G11C11/403 , G11C11/40603 , G11C11/4076
摘要： A method and apparatus for refreshing a row of a memory device prior to a scheduled refresh. A memory array may include a plurality of memory cells. The memory array may be configured to be refreshed at a first refresh time interval. The memory device may also include an intermediate refresh circuit. The intermediate refresh circuit may be configured to detect a triggering event and request a refresh for a row of the memory array in response to detecting a triggering event.

5. 发明授权

US09251054B2 Implementing enhanced reliability of systems utilizing dual port DRAM 有权
标题翻译：实现利用双端口DRAM的系统的增强的可靠性
公开(公告)号：US09251054B2
公开(公告)日：2016-02-02
申请号：US14227187
申请日：2014-03-27
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Carlos A. Fernandez , Joab D. Henderson , Jeffrey A. Sabrowski , Anuwat Saetow , Saravanan Sethuraman
IPC分类号： G06F11/00 , G06F12/02 , G06F11/10
CPC分类号： G06F12/0238 , G06F11/073 , G06F11/0793 , G06F11/1044 , G06F11/1048 , G06F11/108 , G06F2212/251
摘要： A method, system and computer program product are provided for implementing enhanced reliability of memory subsystems utilizing a dual port Dynamic Random Access Memory (DRAM) configuration. The DRAM configuration includes a first buffer and a second buffer, each buffer including a validity counter. The validity counter for a receiving buffer is incremented as each respective data row from a transferring buffer is validated through Error Correction Code (ECC), Reliability, Availability, and Serviceability (RAS) logic and transferred to the receiving buffer, while the validity counter for the transferring buffer is decremented. Data are read from or written to either the first buffer or the second buffer based upon a respective count value of the validity counters.
摘要翻译：提供了一种方法，系统和计算机程序产品，用于利用双端口动态随机存取存储器（DRAM）配置来实现存储器子系统的增强的可靠性。 DRAM配置包括第一缓冲器和第二缓冲器，每个缓冲器包括有效性计数器。接收缓冲器的有效性计数器随着来自传送缓冲器的每个相应数据行通过纠错码（ECC），可靠性，可用性和可服务性（RAS）逻辑被验证并递送到接收缓冲器而增加，而有效性计数器传送缓冲区递减。基于有效性计数器的相应计数值，从第一缓冲器或第二缓冲器读取或写入数据。

6. 发明申请

US20150370706A1 METHOD AND APPARATUS FOR CACHE MEMORY DATA PROCESSING 有权
公开(公告)号：US20150370706A1
公开(公告)日：2015-12-24
申请号：US14307648
申请日：2014-06-18
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , David M. Daly , Robert K. Montoye , Saravanan Sethuraman , Diyanesh B. Chinnakkonda Vidyapoornachary
IPC分类号： G06F12/08 , G06F13/40 , G06F9/455 , G06F13/16
CPC分类号： G06F12/0811 , G06F3/00 , G06F9/45558 , G06F9/50 , G06F12/0833 , G06F13/1673 , G06F13/4045 , G06F2009/45583 , G06F2212/1016 , G06F2212/283 , G06F2212/62
摘要： Apparatus and methods are disclosed that enable the allocation of a cache portion of a memory buffer to be utilized by an on-cache function controller (OFC) to execute processing functions on “main line” data. A particular method may include receiving, at a memory buffer, a request from a memory controller for allocation of a cache portion of the memory buffer. The method may also include acquiring, by an on-cache function controller (OFC) of the memory buffer, the requested cache portion of the memory buffer. The method may further include executing, by the OFC, a processing function on data stored at the cache portion of the memory buffer.

7. 发明申请

US20150269096A1 SYSTEM AND METHOD FOR COMPUTER MEMORY WITH LINKED PATHS 有权
公开(公告)号：US20150269096A1
公开(公告)日：2015-09-24
申请号：US14220617
申请日：2014-03-20
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Girisankar Paulraj , Diyanesh B. Chinnakkonda Vidyapoornachary
IPC分类号： G06F13/16
CPC分类号： G06F13/1673 , G06F3/065 , G06F12/0246 , G06F2212/7203 , G06F2212/7208 , Y02D10/14
摘要： A first memory buffer has a first high speed memory channel and a second high speed memory channel. A second memory buffer is connected to the first memory buffer through a first connection. The second memory buffer has a third high speed memory channel and a fourth high speed memory channel. The first connection connects the first high speed memory channel and the third high speed memory channel. A first memory controller is connected to the first memory buffer through the second high speed memory channel. A second memory controller is connected to the second memory buffer through a second connection. The second connection is connected to the second memory buffer through the fourth high speed memory channel. A first memory module set is connected to the first memory buffer and a second memory module set is connected to the second memory buffer.

8. 发明申请

US20150228328A1 REFERENCE VOLTAGE MODIFICATION IN A MEMORY DEVICE 有权
标题翻译：存储器件中的参考电压修改
公开(公告)号：US20150228328A1
公开(公告)日：2015-08-13
申请号：US14694067
申请日：2015-04-23
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Joab D. Henderson , Kyu-hyoun Kim , Jeffrey A. Sabrowski , Anuwat Saetow
IPC分类号： G11C11/4099 , G11C11/4076 , G11C11/4091 , G11C11/406
CPC分类号： G11C11/406 , G11C11/4076 , G11C11/4091 , G11C11/4099
摘要： A method and apparatus for modifying a reference voltage between refreshes in a memory device are disclosed. The memory array may include a plurality of memory cells. The memory device may also include a sense amplifier. The sense amplifier may be configured to read data from the plurality of memory cells using a reference voltage. The memory device may also include a sense amplifier reference voltage modification circuit. The sense amplifier reference voltage modification circuit may be configured to detect a triggering event and modify the reference voltage in response to detecting a triggering event.
摘要翻译：公开了一种用于修改存储器件中的刷新之间的参考电压的方法和装置。存储器阵列可以包括多个存储器单元。存储器件还可以包括读出放大器。读出放大器可以被配置为使用参考电压从多个存储单元读取数据。存储器件还可以包括读出放大器参考电压修改电路。感测放大器参考电压修改电路可以被配置为响应于检测到触发事件来检测触发事件并修改参考电压。

9. 发明授权

US09037948B2 Error correction for memory systems 有权
标题翻译：内存系统错误更正
公开(公告)号：US09037948B2
公开(公告)日：2015-05-19
申请号：US13799986
申请日：2013-03-13
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Marc A. Gollub , Girisankar Paulraj , Diyanesh B. Vidyapoornachary
IPC分类号： G11C29/00 , G06F11/14
CPC分类号： G06F11/1469 , G06F11/073 , G06F11/0793 , G06F11/1048
摘要： According to one embodiment, a method for error correction in a memory module having ranks is provided where each rank has memory devices. The method includes determining a first mark condition for a first rank of the memory module, the first mark condition based on one or more uncorrectable error occurring in a first memory device in the first rank, placing a first mark in the first memory device, determining a second mark condition for the first rank, the second mark condition based on one or more uncorrectable error occurring in a second memory device in the first rank, placing a second mark in a third memory device in a second rank of the memory module and configuring the first memory device to respond to commands directed to the second rank, wherein configuring the first memory device is based on placing of the first mark and the second mark.
摘要翻译：根据一个实施例，提供了一种具有等级的存储器模块中的纠错方法，其中每个等级具有存储器件。该方法包括基于在第一等级的第一存储器件中发生的一个或多个不可校正错误来确定存储器模块的第一等级的第一标记条件，第一标记条件，将第一标记放置在第一存储器件中，确定第一等级的第二标记条件，基于在第一等级中的第二存储器件中发生的一个或多个不可校正错误的第二标记条件，将第二标记放置在存储器模块的第二等级中的第三存储器件中，并且配置用于响应指向第二等级的命令的第一存储器设备，其中配置第一存储器设备基于放置第一标记和第二标记。

10. 发明申请

US20150033002A1 REQUESTING MEMORY SPACES AND RESOURCES USING A MEMORY CONTROLLER 审中-公开
标题翻译：使用存储器控制器来请求存储空间和资源
公开(公告)号：US20150033002A1
公开(公告)日：2015-01-29
申请号：US13948290
申请日：2013-07-23
申请人： International Business Machines Corporation
发明人： Edgar R. Cordero , Varkey K. Varghese , Diyanesh B. Vidyapoornachary
IPC分类号： G06F9/50
CPC分类号： G06F12/023 , G06F9/4401 , G06F9/45558 , G06F9/5016 , G06F11/073 , G06F12/08 , G06F13/24 , G06F2009/45579 , G06F2212/1044
摘要： Methods of requesting memory spaces and resources using a memory controller are provided. A particular method may include communicating, by a memory controller, a request to a computer program for a resource, and using the resource in response to an indication from the computer program that the resource is available. Another particular method may include communicating a request to a memory controller for at least one of a memory space of a memory or a second resource. The memory controller may be configured to communicate the request from the first resource to a computer program. Another particular method may also include using, by the first resource, at least one of the memory space or the second resource in response to an indication that the memory space or the second resource is available.
摘要翻译：提供了使用存储器控制器请求存储器空间和资源的方法。特定方法可以包括由存储器控制器向计算机程序发送对资源的请求，并且响应于来自计算机程序的指示使用该资源资源可用。另一特定方法可以包括向存储器控制器传送对于存储器或第二资源的存储器空间中的至少一个的请求。存储器控制器可以被配置为将来自第一资源的请求传达到计算机程序。另一特定方法还可以包括响应于存储器空间或第二资源可用的指示，由第一资源使用存储器空间或第二资源中的至少一个。

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