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41. 发明授权

US11244949B2 Semiconductor device having stacked transistor pairs and method of forming same 有权
公开(公告)号：US11244949B2
公开(公告)日：2022-02-08
申请号：US16441725
申请日：2019-06-14
申请人： IMEC vzw
发明人： Pieter Weckx , Juergen Boemmels , Julien Ryckaert
IPC分类号： H01L29/76 , H01L27/11 , G11C5/02 , G11C5/06 , G11C11/412 , H01L21/822 , H01L21/8238
摘要： The disclosed technology generally relates to semiconductor devices and more particularly to a semiconductor device comprising stacked complementary transistor pairs. In one aspect, a semiconductor device comprises first and second sets of transistors comprising a pass transistor and a stacked complementary transistor pair of a lower transistor and an upper transistor, wherein first transistor comprises a semiconductor channel extending along a horizontal first fin track, and each second transistor comprises a semiconductor channel extending along a second fin track parallel to the first fin track, and wherein the semiconductor channels of the pass transistors and of the lower transistors are arranged at a first level and the semiconductor channels of said upper transistors are arranged at a second level, a first tall gate electrode forming a common gate for the first complementary transistor pair and arranged along a horizontal first gate track, and a first short gate electrode forming a gate for the first pass transistor and arranged along a second gate track, a second tall gate electrode forming a common gate for the second complementary transistor pair and arranged along the second gate track, a second short gate electrode forming a gate for the second pass transistor and arranged along the first gate track, first and second contact arrangements forming a common drain contact for the transistors of the first set and the second set, respectively, and first and second cross-couple contacts extending horizontally between and interconnecting the first tall gate electrode and the second contact arrangement, and the second tall gate electrode and the first contact arrangement, respectively.

42. 发明授权

US11195921B2 Semiconductor device with silicon carbide body 有权
公开(公告)号：US11195921B2
公开(公告)日：2021-12-07
申请号：US16412131
申请日：2019-05-14
申请人： Infineon Technologies AG
发明人： Ralf Siemieniec , Thomas Aichinger , Romain Esteve , Ravi Keshav Joshi , Shiqin Niu
IPC分类号： H01L29/76 , H01L29/16 , H01L29/66 , H01L29/423 , H01L29/78
摘要： A semiconductor device includes a gate electrode and a gate dielectric. The gate electrode extends from a first surface of a silicon carbide body into the silicon carbide body. The gate dielectric is between the gate electrode and the silicon carbide body. The gate electrode includes a metal structure and a semiconductor layer between the metal structure and the gate dielectric.

43. 发明授权

US11195834B2 Semiconductor device having deep wells 有权
公开(公告)号：US11195834B2
公开(公告)日：2021-12-07
申请号：US16866506
申请日：2020-05-04
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Meng-Han Lin , Chih-Ren Hsieh , Chen-Chin Liu
IPC分类号： H01L29/76 , H01L27/092 , H01L27/11546 , H01L27/11526 , H01L27/11575 , H01L29/10 , H01L21/266 , H01L21/761 , H01L21/762 , H01L21/8234 , H01L21/8238
摘要： A semiconductor device includes first and second voltage device regions and a deep well common to the first and second voltage device regions. An operation voltage of electronic devices in the second voltage device region is higher than that of electronic devices in the first voltage device region. The deep well has a first conductivity type. The first voltage device region includes a first well having the second conductivity type and a second well having the first conductivity type. The second voltage region includes a third well having a second conductivity type and a fourth well having the first conductivity type. A second deep well having the second conductivity type is formed below the fourth well. The first, second and third wells are in contact with the first deep well, and the fourth well is separated by the second deep well from the first deep well.

44. 发明申请

US20210376134A1 SEMICONDUCTOR DEVICE 有权
公开(公告)号：US20210376134A1
公开(公告)日：2021-12-02
申请号：US17403347
申请日：2021-08-16
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Tse-An CHEN , Lain-Jong LI , Wen-Hao CHANG , Chien-Chih TSENG
IPC分类号： H01L29/76 , H01L29/24 , H01L21/02 , H01L29/66 , H01L27/12 , H01L21/78
摘要： A semiconductor device includes a substrate, a channel layer, an insulating layer, source/drain contacts, a gate dielectric layer, and a gate electrode. The channel layer over the substrate and includes two dimensional (2D) material. The insulating layer is on the channel layer. The source/drain contacts are over the channel layer. The gate dielectric layer is over the insulating layer and the channel layer. The gate electrode is over the gate dielectric layer and between the source/drain contacts.

45. 发明申请

US20210375627A1 SEMICONDUCTOR DEVICE WITH TWO-DIMENSIONAL MATERIALS 有权
公开(公告)号：US20210375627A1
公开(公告)日：2021-12-02
申请号：US17078247
申请日：2020-10-23
申请人： Taiwan Semiconductor Manufacturing Co., Ltd.
发明人： Tse-An CHEN , Lain-Jong LI
IPC分类号： H01L21/18 , H01L21/02 , H01L21/683 , H01L21/78 , H01L29/66 , H01L29/20 , H01L29/24 , H01L29/76
摘要： The present disclosure describes a method that includes forming a first two-dimensional (2D) layer on a first substrate and attaching a second 2D layer to a carrier film. The method also includes bonding the second 2D layer to the first 2D layer to form a heterostack including the first and second 2D layers. The method further includes separating the first 2D layer of the heterostack from the first substrate and attaching the heterostack to a second substrate. The method further includes removing the carrier film from the second 2D layer.

46. 发明授权

US11183593B2 Three-dimensional field effect device 有权
公开(公告)号：US11183593B2
公开(公告)日：2021-11-23
申请号：US16592389
申请日：2019-10-03
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Huimei Zhou , Su Chen Fan , Shogo Mochizuki , Peng Xu , Nicolas J. Loubet
IPC分类号： H01L29/76 , H01L29/94 , H01L31/062 , H01L29/78 , H01L29/66 , H01L27/092 , H01L27/06 , H01L29/08
摘要： A method of forming stacked fin field effect devices is provided. The method includes forming a layer stack on a substrate, wherein the layer stack includes a first semiconductor layer on a surface of the substrate, a second semiconductor layer on the first semiconductor layer, a third semiconductor layer on the second semiconductor layer, a separation layer on the third semiconductor layer, a fourth semiconductor layer on the separation layer, a fifth semiconductor layer on the fourth semiconductor layer, and a sixth semiconductor layer on the fifth semiconductor layer. The method further includes forming a plurality of channels through the layer stack to the surface of the substrate, and removing portions of the second semiconductor layer and fifth semiconductor layer to form lateral grooves.

47. 发明授权

US11177372B2 Stacked vertical transport field effect transistor electrically erasable programmable read only memory (EEPROM) devices 有权
公开(公告)号：US11177372B2
公开(公告)日：2021-11-16
申请号：US16671844
申请日：2019-11-01
申请人： INTERNATIONAL BUSINESS MACHINES CORPORATION
发明人： Karthik Balakrishnan , Jeng-Bang Yau , Alexander Reznicek , Tak H. Ning
IPC分类号： H01L29/76 , H01L29/94 , H01L29/66 , H01L29/423 , H01L27/11521 , H01L29/08 , H01L29/06 , H01L29/78
摘要： A vertically stacked set of an n-type vertical transport field effect transistor (n-type VT FET) and a p-type vertical transport field effect transistor (p-type VT FET) is provided. The vertically stacked set of the n-type VT FET and the p-type VT FET includes a first bottom source/drain layer on a substrate, that has a first conductivity type, a lower channel pillar on the first bottom source/drain layer, and a first top source/drain on the lower channel pillar, that has the first conductivity type. The vertically stacked set of the n-type VT FET and the p-type VT FET further includes a second bottom source/drain on the first top source/drain, that has a second conductivity type different from the first conductivity type, an upper channel pillar on the second bottom source/drain, and a second top source/drain on the upper channel pillar, that has the second conductivity type.

48. 发明申请

US20210343845A1 QUANTUM DOT ARRAY DEVICES WITH SHARED GATES 有权
公开(公告)号：US20210343845A1
公开(公告)日：2021-11-04
申请号：US17368427
申请日：2021-07-06
申请人： Intel Corporation
发明人： Hubert C. George , Ravi Pillarisetty , Jeanette M. Roberts , Nicole K. Thomas , James S. Clarke
IPC分类号： H01L29/40 , H01L29/12 , H01L29/66 , H01L29/423 , H01L29/76 , H01L23/532 , B82Y40/00 , B82Y10/00
摘要： Disclosed herein are quantum dot devices, as well as related computing devices and methods. For example, in some embodiments, a quantum dot device may include: a quantum well stack structure of a quantum dot device, wherein the quantum well stack structure includes an insulating material to define multiple rows of quantum dot formation regions; and a gate that extends over multiple ones of the rows.

49. 发明申请

US20210320173A1 DEFORMABLE ELECTRONIC DEVICE AND METHOD OF MAKING A DEFORMABLE ELECTRONIC DEVICE 有权
公开(公告)号：US20210320173A1
公开(公告)日：2021-10-14
申请号：US17226331
申请日：2021-04-09
申请人： THE BOARD OF TRUSTEES OF THE UNIVERSITY OF ILLINOIS
发明人： Pinshane Huang , Arend van der Zande , Elif Ertekin , Edmund Han , Jaehyung Yu , Mohammad Abir Hossain
IPC分类号： H01L29/06 , H01L29/76 , H01L29/16 , H01L29/22 , H01L29/24
摘要： A method of making a deformable electronic device comprises forming a multilayer device structure comprising functional layers on a flexible substrate. At least one, some or all of the functional layers comprises a stack of 2D monolayers, and a number or proportion of misaligned interfaces within each stack of 2D monolayers is controlled to obtain a predetermined bending stiffness. Each of the misaligned interfaces comprises a twist angle and/or lattice mismatch between adjacent 2D monolayers. The functional layers may include electronically active layers and other layers having a dielectric, insulating, and/or protective function.

50. 发明授权

US11145709B2 Semiconductor device including a capacitor 有权
公开(公告)号：US11145709B2
公开(公告)日：2021-10-12
申请号：US16439636
申请日：2019-06-12
申请人： TAIWAN SEMICONDUCTOR MANUFACTURING CO., LTD.
发明人： Hong-Yang Chen , Tian Sheng Lin , Yi-Cheng Chiu , Hung-Chou Lin , Yi-Min Chen , Kuo-Ming Wu , Chiu-Hua Chung
IPC分类号： H01L27/108 , H01L29/76 , H01L31/119 , H01L49/02 , H01L27/01 , H01L27/06
摘要： A capacitor structure for a power semiconductor device includes a semiconductor substrate, an isolation insulating layer having a ring-shape and including an outer periphery and an inner periphery defining an opening region, a first electrode disposed on the isolation insulating layer, a dielectric layer disposed on the first electrode, and a second electrode disposed on the dielectric layer.

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